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公开(公告)号：US12101088B2
公开(公告)日：2024-09-24
申请号：US17938733
申请日：2022-10-07
发明人： Weiqiang Xu , Chengqun Wang , Yanjuan Shang
CPC分类号： H03K19/017509 , G06F13/36 , H03K3/037 , H03K17/005 , H03K23/40 , G06F2213/40
摘要： The present invention provides a frequency-halving latch circuit for deterministic field bus network data forwarding and application thereof. The frequency-halving latch circuit includes a data buffer equipped with two buffer units; a frequency-halving enable latch signal generation module for generating a first frequency-halving latch signal and a second frequency-halving latch signal with opposite levels, and selecting data buffer units of the data buffer based on the first frequency-halving latch signal, the second frequency-halving latch signal and a receiving enable signal; and a shift register including a first trigger and a second trigger which are initialized to opposite output states, the first trigger and the second trigger is connected to realize a shift operation, and data stored in the data buffer units is finally selected and read based on a low order in the shift register composed of the two triggers and a read enable signal. The frequency-halving latch circuit can be applied to a scenario of deterministic field bus network data forwarding as a same-frequency out-of-phase data cross-clock domain circuit, with high resource utilization rate and stability.
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公开(公告)号：US12099519B1
公开(公告)日：2024-09-24
申请号：US17548291
申请日：2021-12-10
发明人： Rishi Baldawa , Siva Swaroop Palli , Arijit Choudhury , Shawn Patrick Jones , Felipe de Aguiar Kamakura , Mukti Ranjan Sahoo
CPC分类号： G06F16/27 , G06F9/542 , G06F13/36 , G06F2213/40
摘要： A system is configured to replicate events to be processed by service regions. The system implements an event bus service that hosts an event bus in respective ones of a plurality of regions. The event bus service is configured to receive, at the event bus in a secondary region of the plurality of regions, a replicated indication of an event that is replicated from the event bus in a primary region of the plurality of regions. The event bus service determines, at the event bus in the secondary region, whether the primary region has completed processing of the event. Based on a determination that the primary region has not completed processing of the event within the pre-determined time period, the event bus service processes the event according to the replicated indication and indicates, in the replication record, that the secondary region has completed processing of the event.
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公开(公告)号：US20240304320A1
公开(公告)日：2024-09-12
申请号：US18601238
申请日：2024-03-11
申请人： Arthrex, Inc.
发明人： Gregory St. Clair , Ken Olbrish , Lee Holoien , Craig Speier , Tim Jackson
CPC分类号： G16H40/63 , G06F13/36 , G06F2213/40
摘要： A surgical control system is in communication with a plurality of surgical devices. In operation, the surgical devices broadcast device data including messages indicative of at least one of a control state and a detected condition associated with the operation of each of the plurality of surgical devices via a communication bus in communication with a plurality of device controllers of the plurality of surgical devices. Image data is captured demonstrating a surgical site and a surgery status is identified in response to the image data. Aggregate data is generated, including the surgery status and the device data, in a packet. The aggregate data is communicated over the communication bus.
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公开(公告)号：US12088302B2
公开(公告)日：2024-09-10
申请号：US18364848
申请日：2023-08-03
申请人： Quantum Machines
发明人： Yonatan Cohen , Nissim Ofek , Itamar Sivan
摘要： A controller comprises a pulse generation circuit, output management circuitry, and a plurality of outputs configured to connect the controller to a plurality of controlled elements. The pulse generation circuit is configured to generate quantum control pulses. For each control pulse of a plurality of control pulses generated by the pulse generation circuit, the output management circuitry is configured to determine to which of the plurality of outputs to route the control pulse such that a first of the plurality of control pulses is routed to a first of the plurality of controlled elements and a second of the plurality of control pulses is routed to a second of the plurality of control elements.
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公开(公告)号：US20240220447A1
公开(公告)日：2024-07-04
申请号：US18610081
申请日：2024-03-19
申请人： Rebellions Inc.
发明人： Wongyu Shin , Juyeong Yoon , Sangeun Je
摘要： A processing device comprises a first set of processors comprising a first processor and a second processor, each of which comprises at least one controllable port, a first memory operably coupled to the first set of processors, at least one forward data line configured for one-way transmission of data in a forward direction between the first set of processors, and at least one backward data line configured for one-way transmission of data in a backward direction between the first set of processors. wherein the first set of processors are operably coupled in series via the at least one forward data line and the at least one backward data line.
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公开(公告)号：US12001363B2
公开(公告)日：2024-06-04
申请号：US17926438
申请日：2021-05-21
申请人： Octavo Systems LLC
CPC分类号： G06F13/36 , G06F15/7807
摘要： A Secure Enclave SiP (SE-SiP) is disclosed. The SE-SiP provides all the security benefits of a system designed using a Trusted Platform Module (TPM), replaces the need to trust a general-purpose CPU chip vendor with the need to trust a much simpler more trustworthy configurable device, and replaces the need to trust the entire system motherboard manufacturer with the much more limited need to trust the SE-SiP manufacturer. It can provide privacy for the software and data sent to the system, resident on it, or retrieved from it, with respect to all parties—including the person/party in physical possession of the device.
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公开(公告)号：US12001362B2
公开(公告)日：2024-06-04
申请号：US17394536
申请日：2021-08-05
摘要： A method, apparatus, and computer program product provide for dynamically reprogrammable topologically unique integrated circuit identification. In an example embodiment, an integrated circuit may be arranged among multiple integrated circuits. The integrated circuit may be configured to derive a topologically unique identifier by performing input measurements of stimuli provided by a host circuit. The integrated circuit may be topologically indistinguishable from at least one other integrated circuit of the multiple integrated circuits from a perspective of the host circuit.
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8.发明公开公开(公告)号：US20240177752A1
公开(公告)日：2024-05-30
申请号：US18434418
申请日：2024-02-06
CPC分类号： G11C7/22 , G06F13/36 , G11C7/10 , G06F13/1689
摘要： Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.
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公开(公告)号：US11995372B2
公开(公告)日：2024-05-28
申请号：US17990239
申请日：2022-11-18
发明人： Kwangbok Lee , Byeongcheol Hyeon , Sangwon Kim , Youngkook Kim , Jeongryeol Seo
CPC分类号： G06F3/1446 , G06F3/147 , G06F13/36 , G06F2213/40
摘要： A display apparatus and a control method therefor are provided. The display apparatus includes: a plurality of display modules; and one or more processors configured to control the plurality of display modules to display an image, wherein a first display module of the plurality of display modules includes a first connector which is connected to the one or more processors, wherein the first display module is configured to receive a first image signal through a first pin of the first connector from the one or more processors, receive a second image signal through a second pin of the first connector, and display an image based on the first image signal, wherein a second display module of the plurality of display modules includes a second connector which is connected to the first display module, wherein the second display module is configured to receive the second image signal through a first pin of the second connector from the first display module, and display an image based on the second image signal, and wherein the second pin of the first connector is electrically connected to the first pin of the second connector.
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公开(公告)号：US11967196B2
公开(公告)日：2024-04-23
申请号：US16764318
申请日：2018-11-19
CPC分类号： G07F17/0064 , A47J36/321 , G06F13/36
摘要： A food preparation appliance and associated components and methods. The food preparation appliance is configured to support transmission of operations updates and other data to/from a local or remote computer. In some embodiments, the food preparation appliance provides a virtual data bus for transmission of the updates or data. The virtual data bus may be bridged to a physical data bus of the food preparation appliance. The food preparation appliance can be configured to receive operations updates regardless of an operational mode of the food preparation appliance.
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