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1.发明授权公开(公告)号：US12021532B2
公开(公告)日：2024-06-25
申请号：US18134331
申请日：2023-04-13
申请人： Quantum Machines
发明人： Yonatan Cohen , Nissim Ofek , Itamar Sivan
IPC分类号： G06N99/00 , G06N10/00 , H03K3/38 , H03K19/195
CPC分类号： H03K3/38 , G06N10/00 , H03K19/195
摘要： A quantum controller comprises a first quantum control pulse generation circuit and a second quantum control pulse generation circuit. The first quantum control pulse generation circuit and a second quantum control pulse generation circuit are operable to operate asynchronously during some time intervals of a quantum algorithm and synchronously during other time intervals of the quantum algorithm.
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公开(公告)号：US12009789B2
公开(公告)日：2024-06-11
申请号：US17081271
申请日：2020-10-27
申请人： IQM Finland Oy
发明人： Juha Hassel , Pasi Lähteenmäki
CPC分类号： H03F19/00 , H03K3/38 , H01L25/0657 , H01L25/105 , H03F2200/447 , H10N69/00
摘要： A cryogenic integrated circuit or integrated module includes a travelling wave parametric amplifier or a Josephson parametric amplifier. The cryogenic integrated circuit or integrated module also includes an oscillator, a signal input, a biasing input, and a signal output. The oscillator is connected to an input of the amplifier and is configured to produce an oscillating drive signal. The signal input couples input signals into the amplifier. The biasing input couples biasing signals into the oscillator. The signal output conveys output signals from the amplifier out of the cryogenic integrated circuit or integrated module.
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公开(公告)号：US11967956B2
公开(公告)日：2024-04-23
申请号：US18101756
申请日：2023-01-26
申请人： Quantum Machines
发明人： Yonatan Cohen , Nissim Ofek , Itamar Sivan , Tal Shani
IPC分类号： H03K3/38 , G06N3/04 , G06N10/00 , H03K19/195
CPC分类号： H03K3/38 , G06N3/04 , G06N10/00 , H03K19/195
摘要： A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.
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公开(公告)号：US11942937B2
公开(公告)日：2024-03-26
申请号：US17736517
申请日：2022-05-04
申请人： Charles Ryan Wallace , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Haitao O. Dai
发明人： Charles Ryan Wallace , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Haitao O. Dai
IPC分类号： H03K19/195 , H03K3/38 , H03K19/17736 , H03K19/20
CPC分类号： H03K19/195 , H03K3/38 , H03K19/1774 , H03K19/17744 , H03K19/20
摘要： Pulse-generator-based reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors include pulse generators having strengthened or weakened bias taps (transformer couplings to RQL AC clock resonators or DC bias lines) as compared to bias taps of Josephson transmission lines in the operational RQL circuitry, or Josephson junctions (JJs) with larger or smaller critical currents as compared to JJs in the operational RQL circuitry. Pulse generators with weakened bias taps or larger JJs can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. The bias-level sensors can be staged by relative strength to indicate whether a provided bias value is an improvement when varied over a range.
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公开(公告)号：US11877523B2
公开(公告)日：2024-01-16
申请号：US17369732
申请日：2021-07-07
发明人： Roman Lutchyn , Michael Freedman , Andrey Antipov
IPC分类号： H01L29/20 , H10N60/84 , H03K3/38 , G06N10/00 , B82Y10/00 , H01L29/66 , H01L29/06 , H10N60/01 , H10N60/30 , H10N60/85 , H10N60/10
CPC分类号： H10N60/84 , B82Y10/00 , G06N10/00 , H01L29/0673 , H01L29/66977 , H03K3/38 , H10N60/01 , H10N60/128 , H10N60/30 , H10N60/85 , H01L29/20
摘要： Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.
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公开(公告)号：US11877522B2
公开(公告)日：2024-01-16
申请号：US17831976
申请日：2022-06-03
IPC分类号： H10N60/12 , G06F30/394 , G06N10/20 , H03K3/38 , H03K19/195 , H03K19/20 , H10N60/80 , G06F119/12
CPC分类号： H10N60/12 , G06F30/394 , G06N10/20 , H03K3/38 , H03K19/195 , H03K19/20 , H10N60/805 , G06F2119/12
摘要： Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.
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公开(公告)号：US11870443B2
公开(公告)日：2024-01-09
申请号：US17853132
申请日：2022-06-29
申请人： Quantum Machines
发明人： Yonatan Cohen , Nissim Ofek , Itamar Sivan
摘要： A system comprises time-tracking circuitry and phase parameter generation circuitry. The time-tracking circuitry is operable to generate a time-tracking value corresponding to time elapsed since a reference time. The phase parameter generation circuitry operable to: receive the time-tracking value; receive a control signal that conveys a frequency parameter corresponding to a desired frequency of an oscillating signal; and generate a plurality of phase parameters used for generation of an oscillating signal, wherein the generation of the plurality of phase parameters is based on the time-tracking value and the frequency parameter such that the oscillating signal maintains phase continuity across changes in the frequency parameter.
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公开(公告)号：US11839164B2
公开(公告)日：2023-12-05
申请号：US16996595
申请日：2020-08-18
申请人： D-WAVE SYSTEMS INC.
IPC分类号： H10N60/12 , G11C11/44 , H03K3/38 , H03K17/92 , G11C8/00 , G06N10/40 , G11C8/10 , H10N60/80 , H10N69/00
CPC分类号： H10N60/12 , G06N10/40 , G11C8/00 , G11C8/10 , G11C11/44 , H03K3/38 , H03K17/92 , H10N60/805 , H10N69/00
摘要： Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.
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公开(公告)号：US11736096B2
公开(公告)日：2023-08-22
申请号：US17725829
申请日：2022-04-21
申请人： Quantum Machines
发明人： Yonatan Cohen , Nissim Ofek , Itamar Sivan
IPC分类号： H03K3/38 , G06N10/00 , H03K19/195
CPC分类号： H03K3/38 , G06N10/00 , H03K19/195
摘要： A system comprises an electromagnetic pulse generation system that comprises a first pulse generation circuit, a second pulse generation circuit, and a mixing circuit. The electromagnetic pulse generation system is operable to output a first pulse generated by the first pulse generation circuit onto a first signal path, output a second pulse generated by the second pulse generation circuit onto the first signal path, generate a third pulse by mixing, via the mixing circuit, a fourth pulse generated by the first pulse generation circuit and a fifth pulse generated by the second pulse generation circuit, and output the third pulse on the first signal path.
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公开(公告)号：US11723288B2
公开(公告)日：2023-08-08
申请号：US17209107
申请日：2021-03-22
申请人： Fu-Chang Hsu , Kevin Hsu
发明人： Fu-Chang Hsu , Kevin Hsu
CPC分类号： H10N60/11 , G06N10/00 , H03K3/38 , H10N60/128 , H10N69/00
摘要： A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.
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