公开(公告)号：US08860482B1

公开(公告)日：2014-10-14

申请号：US13918739

申请日：2013-06-14

Applicant: Altera Corporation

Inventor： Xiong Liu ,  Thungoc Tran ,  Tim Tri Hoang ,  Wilson Wong

IPC: H03L7/06 ,  H03L7/099

CPC classification number: H03L7/099 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase-locked loop circuit includes an oscillator circuit that generates a clock signal. The oscillator circuit has gears. Each of the gears of the oscillator circuit corresponds to a respective frequency range of the clock signal. A gear control circuit includes a regulator circuit that provides a supply voltage to the oscillator circuit. Each of the gears of the oscillator circuit corresponds to a different supply voltage provided by the regulator circuit. The regulator circuit varies the supply voltage to change a selected one of the gears of the oscillator circuit. The gear control circuit varies the supply voltage for one of the gears of the oscillator circuit to adjust a frequency range of that gear of the oscillator circuit.

Abstract translation: 锁相环电路包括产生时钟信号的振荡电路。 振荡电路有齿轮。 振荡器电路的每个齿轮对应于时钟信号的相应频率范围。 齿轮控制电路包括向振荡器电路提供电源电压的调节器电路。 振荡器电路的每个齿轮对应于由调节器电路提供的不同的电源电压。 调节器电路改变电源电压以改变振荡器电路的所选齿轮。 齿轮控制电路改变振荡器电路的一个齿轮的电源电压，以调整振荡器电路的该齿轮的频率范围。

公开(公告)号：US09383763B1

公开(公告)日：2016-07-05

申请号：US14146913

申请日：2014-01-03

Applicant: Altera Corporation

Inventor： Xiong Liu ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Wilson Wong ,  Vishal Giridharan

IPC: G05F3/26

CPC classification number: G05F3/262 ,  G05F3/26

Abstract: In one embodiment, an integrated circuit current mirror circuit is disclosed. The integrated circuit current mirror circuit includes a reference circuit, an output circuit and a mode selector circuit. The reference circuit includes an input terminal that receives a reference current. The output circuit generates an output current that is proportional to the reference current. The output circuit is coupled to a load circuit. The output current is provided to the load circuit. The mode selector circuit is coupled to the reference circuit and the output circuit. The mode selector circuit receives a plurality of mode control signals having different voltage levels. The mode selector circuit selects one of the mode control signals. The selected mode control signal is routed to the reference circuit and the output circuit to place the current mirror circuit in a desired mode.

Abstract translation: 在一个实施例中，公开了集成电路电流镜电路。 集成电路电流镜电路包括参考电路，输出电路和模式选择器电路。 参考电路包括接收参考电流的输入端。 输出电路产生与参考电流成比例的输出电流。 输出电路耦合到负载电路。 输出电流被提供给负载电路。 模式选择器电路耦合到参考电路和输出电路。 模式选择器电路接收具有不同电压电平的多个模式控制信号。 模式选择器电路选择模式控制信号之一。 所选择的模式控制信号被路由到参考电路和输出电路以将电流镜像电路置于期望的模式。

公开(公告)号：US08837571B1

公开(公告)日：2014-09-16

申请号：US13958395

申请日：2013-08-02

Applicant: Altera Corporation

Inventor： Yanjing Ke ,  Thungoc M Tran ,  Weiqi Ding ,  Jie Shen ,  Xiong Liu ,  Sangeeta Raman ,  Peng Li

IPC: H03K5/159 ,  H04L27/01

CPC classification number: H04L25/03057 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L2025/03356

Abstract: One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及具有判决反馈均衡和在线仪器的接收机。 时钟数据恢复循环从输入信号获得恢复的时钟信号，并且由恢复的时钟信号触发的第一采样器从输入信号产生恢复的数据信号。 相位内插器接收恢复的时钟信号并产生相位插值时钟信号。 第二取样器由判定反馈均衡模式中的恢复的时钟信号和在片上仪器模式下的相位插值时钟信号触发。 还公开了其它实施例和特征。