公开(公告)号：US10911164B2

公开(公告)日：2021-02-02

申请号：US16140292

申请日：2018-09-24

Applicant: Altera Corporation

Inventor： Neville Carvalho ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC: H04B17/21 ,  H04B17/11 ,  G01R35/00 ,  G12B13/00

Abstract: The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is 10 configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

公开(公告)号：US20170214557A1

公开(公告)日：2017-07-27

申请号：US15483881

申请日：2017-04-10

Applicant: Altera Corporation

Inventor： Tim Tri Hoang ,  Nam V. Nguyen

IPC: H04L25/03 ,  H04B3/14

CPC classification number: H04L25/03885 ,  H03G3/002 ,  H04B1/16 ,  H04B3/143 ,  H04L5/006 ,  H04L25/03 ,  H04L25/03019 ,  H04L25/03057

Abstract: Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry is operable to generate a digital signal to change a gain setting of the receiver. When the signal at the receiver's output is under-equalized, the AC gain of the receiver is increased. When the signal at the receiver's output is over-equalized, the AC gain of the receiver is decreased.

公开(公告)号：US09680469B1

公开(公告)日：2017-06-13

申请号：US15156309

申请日：2016-05-16

Applicant: Altera Corporation

Inventor： Kok Siang Tan ,  Tim Tri Hoang

IPC: H03K19/16 ,  H03K19/00 ,  H03K17/687

CPC classification number: H03K19/0005 ,  H03H11/28 ,  H03K17/687 ,  H03K19/17724 ,  H04L25/0278 ,  H04L25/028

Abstract: A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration control circuit adjusts an equivalent resistance of the transistors in the driver circuit based on the comparison output in the calibration mode. The equivalent resistance of the transistors in the driver circuit can be adjusted to support the transmission of data according to multiple different data transmission protocols using transmission links having different characteristic impedances. The equivalent resistance of the transistors in the driver circuit can also be adjusted to compensate for resistance in the package routing conductors and/or to compensate for parasitic resistance.

公开(公告)号：US09383763B1

公开(公告)日：2016-07-05

申请号：US14146913

申请日：2014-01-03

Applicant: Altera Corporation

Inventor： Xiong Liu ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Wilson Wong ,  Vishal Giridharan

IPC: G05F3/26

CPC classification number: G05F3/262 ,  G05F3/26

Abstract: In one embodiment, an integrated circuit current mirror circuit is disclosed. The integrated circuit current mirror circuit includes a reference circuit, an output circuit and a mode selector circuit. The reference circuit includes an input terminal that receives a reference current. The output circuit generates an output current that is proportional to the reference current. The output circuit is coupled to a load circuit. The output current is provided to the load circuit. The mode selector circuit is coupled to the reference circuit and the output circuit. The mode selector circuit receives a plurality of mode control signals having different voltage levels. The mode selector circuit selects one of the mode control signals. The selected mode control signal is routed to the reference circuit and the output circuit to place the current mirror circuit in a desired mode.

Abstract translation: 在一个实施例中，公开了集成电路电流镜电路。 集成电路电流镜电路包括参考电路，输出电路和模式选择器电路。 参考电路包括接收参考电流的输入端。 输出电路产生与参考电流成比例的输出电流。 输出电路耦合到负载电路。 输出电流被提供给负载电路。 模式选择器电路耦合到参考电路和输出电路。 模式选择器电路接收具有不同电压电平的多个模式控制信号。 模式选择器电路选择模式控制信号之一。 所选择的模式控制信号被路由到参考电路和输出电路以将电流镜像电路置于期望的模式。

公开(公告)号：US09231631B1

公开(公告)日：2016-01-05

申请号：US14311192

申请日：2014-06-20

Applicant: Altera Corporation

Inventor： Yanjing Ke ,  Tim Tri Hoang

IPC: H03K19/003 ,  H03K19/0175 ,  H04B1/10 ,  H04L25/02 ,  H03K19/00

CPC classification number: H04B1/1036 ,  H03K19/0005 ,  H03K19/00361 ,  H04B2001/1045 ,  H04L25/0278 ,  H04L25/0286

Abstract: A driver circuit includes unit slice circuits that generate an output data signal based on an input data signal. The driver circuit reduces a voltage swing of the output data signal without changing a termination resistance of the driver circuit in response to decreasing a number of the unit slice circuits that generate the output data signal based on the input data signal.

Abstract translation: 驱动器电路包括基于输入数据信号产生输出数据信号的单位片电路。 响应于基于输入数据信号减少产生输出数据信号的单位片电路的数量，驱动电路降低了输出数据信号的电压摆幅，而不改变驱动电路的终端电阻。

公开(公告)号：US09136949B1

公开(公告)日：2015-09-15

申请号：US14175389

申请日：2014-02-07

Applicant: Altera Corporation

Inventor： Shou-Po Shih ,  Tim Tri Hoang ,  Kazi Asaduzzaman

IPC: G06F1/04 ,  G06F1/12 ,  H04B10/61

CPC classification number: H04B10/6165 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H03L7/14 ,  H04L7/0004 ,  H04L7/0083 ,  H04L7/033

Abstract: A circuit includes a phase detector circuit and a data detection circuit. The phase detector circuit generates first and second phase detection signals based on a data signal and a periodic signal. The data detection circuit includes logic circuitry that generates a logic signal based on the first and second phase detection signals. The data detection circuit also includes a plurality of delay elements that generate a series of delayed detection signals based on the logic signal. The data detection circuit generates a data detection signal indicating when the data signal contains data based on the series of delayed detection signals.

Abstract translation: 电路包括相位检测器电路和数据检测电路。 相位检测器电路基于数据信号和周期信号产生第一和第二相位检测信号。 数据检测电路包括基于第一和第二相位检测信号产生逻辑信号的逻辑电路。 数据检测电路还包括多个基于逻辑信号产生一系列延迟检测信号的延迟元件。 数据检测电路产生指示数据信号何时包含基于一系列延迟检测信号的数据的数据检测信号。

公开(公告)号：US09112655B1

公开(公告)日：2015-08-18

申请号：US13954751

申请日：2013-07-30

Applicant: Altera Corporation

Inventor： Tim Tri Hoang ,  Weiqi Ding ,  Sangeeta Raman ,  Richard Hernandez

IPC: H04L25/38 ,  H04L7/00

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H04L1/20 ,  H04L7/0025 ,  H04L7/033

Abstract: Integrated circuits with high-speed communications capabilities are provided. Such types of integrated circuits may include clock data recovery (CDR) circuitry. The CDR circuitry may receive incoming data and may generate multiple clock signals that are used to latch the incoming data. The CDR circuitry may include data latching circuitry for separately latching even and odd data bits in alternating clock cycles. In particular, the data latching circuitry may be controlled using first, second, third, and fourth clock signals having different respective phase settings. The first and second clock signals may be used to capture even and odd data bits, respectively. The third and fourth clock signals may be used to sample data near the transition between the even and odd data bits. The phase of the first and second clock signals may be dynamically adjusted. The phase setting that yields the optimal link performance may be selected for normal operation.

Abstract translation: 提供了具有高速通信能力的集成电路。 这种类型的集成电路可以包括时钟数据恢复（CDR）电路。 CDR电路可以接收输入数据并且可以生成用于锁存输入数据的多个时钟信号。 CDR电路可以包括数据锁存电路，用于在交替的时钟周期中分别锁存偶数和奇数数据位。 特别地，可以使用具有不同相应相位设置的第一，第二，第三和第四时钟信号来控制数据锁存电路。 第一和第二时钟信号可分别用于捕获偶数和奇数数据位。 第三和第四时钟信号可用于在偶数和奇数数据位之间的转换附近采样数据。 可以动态地调整第一和第二时钟信号的相位。 可以选择产生最佳链路性能的相位设置用于正常操作。

公开(公告)号：US09025656B1

公开(公告)日：2015-05-05

申请号：US14106389

申请日：2013-12-13

Applicant: Altera Corporation

Inventor： Sangeeta Raman ,  Tim Tri Hoang ,  Wilson Wong ,  Jie Shen

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/03019 ,  H04L25/03146 ,  H04L2025/03566 ,  H04L2025/03579 ,  H04L2025/03585

Abstract: The present disclosure provides a floating-tap decision feedback equalization (DFE) circuit. In an exemplary implementation, the floating-tap DFE circuit may include a high-speed shift register, a deserializer and data selector, a bypass deserializer, a high-speed multiplexer and a tap generation circuit. In one aspect of the invention, the floating-tap DFE circuit may advantageously cover an entire tap range beyond a fixed tap range without holes over a range of data rates. Other embodiments, aspects and features are also disclosed.

Abstract translation: 本公开提供浮动抽头判决反馈均衡（DFE）电路。 在示例性实现中，浮动抽头DFE电路可以包括高速移位寄存器，解串器和数据选择器，旁路解串器，高速多路复用器和抽头生成电路。 在本发明的一个方面，浮动抽头DFE电路可有利地覆盖超过一定范围的数据速率的无孔的固定抽头范围的整个抽头范围。 还公开了其它实施例，方面和特征。

公开(公告)号：US20140269890A1

公开(公告)日：2014-09-18

申请号：US13974297

申请日：2013-08-23

Applicant: Altera Corporation

Inventor： Tim Tri Hoang ,  Nam V. Nguyen

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H03G3/002 ,  H04B1/16 ,  H04B3/143 ,  H04L5/006 ,  H04L25/03 ,  H04L25/03019 ,  H04L25/03057

Abstract: Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry is operable to generate a digital signal to change a gain setting of the receiver. When the signal at the receiver's output is under-equalized, the AC gain of the receiver is increased. When the signal at the receiver's output is over-equalized, the AC gain of the receiver is decreased.

Abstract translation: 提供了用于调整接收机增益的系统和方法。 适应电路可操作以基于从接收器的输出的水平和垂直扫描产生的接收器的输出的矩阵表示来识别接收器的输出的眼图。 适配电路还可操作以确定眼睛开口的尺寸是否需要改变。 当确定眼睛开口的尺寸需要改变时，自适应电路可操作以产生数字信号以改变接收器的增益设置。 当接收机输出端的信号欠均衡时，接收机的交流增益增加。 当接收机输出端的信号过均衡时，接收机的交流增益减小。

公开(公告)号：US09654123B1

公开(公告)日：2017-05-16

申请号：US15138749

申请日：2016-04-26

Applicant: ALTERA CORPORATION

Inventor： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding

IPC: H03L7/06 ,  H03L7/23 ,  H03L7/08

CPC classification number: H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

Abstract: One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit including a first strip of PLL circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. Other embodiments and features are also disclosed.