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公开(公告)号：US09383763B1
公开(公告)日：2016-07-05
申请号：US14146913
申请日：2014-01-03
Applicant: Altera Corporation
Inventor： Xiong Liu , Thungoc M. Tran , Tim Tri Hoang , Wilson Wong , Vishal Giridharan
IPC: G05F3/26
Abstract: In one embodiment, an integrated circuit current mirror circuit is disclosed. The integrated circuit current mirror circuit includes a reference circuit, an output circuit and a mode selector circuit. The reference circuit includes an input terminal that receives a reference current. The output circuit generates an output current that is proportional to the reference current. The output circuit is coupled to a load circuit. The output current is provided to the load circuit. The mode selector circuit is coupled to the reference circuit and the output circuit. The mode selector circuit receives a plurality of mode control signals having different voltage levels. The mode selector circuit selects one of the mode control signals. The selected mode control signal is routed to the reference circuit and the output circuit to place the current mirror circuit in a desired mode.
Abstract translation: 在一个实施例中，公开了集成电路电流镜电路。 集成电路电流镜电路包括参考电路，输出电路和模式选择器电路。 参考电路包括接收参考电流的输入端。 输出电路产生与参考电流成比例的输出电流。 输出电路耦合到负载电路。 输出电流被提供给负载电路。 模式选择器电路耦合到参考电路和输出电路。 模式选择器电路接收具有不同电压电平的多个模式控制信号。 模式选择器电路选择模式控制信号之一。 所选择的模式控制信号被路由到参考电路和输出电路以将电流镜像电路置于期望的模式。
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公开(公告)号：US09094239B1
公开(公告)日：2015-07-28
申请号：US13632263
申请日：2012-10-01
Applicant: Altera Corporation
Inventor： Mei Luo , Thungoc M. Tran
CPC classification number: H04L25/0292 , H04L25/03057 , H04L25/03885
Abstract: Among other things, the present invention addresses timing issues related to a polarity control scheme in DFE implementation. Multiplexing that may be necessary for implementing a polarity control scheme is incorporated into multiplexing that may be required to convert half rate data into full rate data in a delay element of a DFE. Clocking signals are provided to a multiplexer that are encoded with polarity information. The various clock signals are generated using a clock generation circuit that incorporates polarity control.
Abstract translation: 其中，本发明涉及与DFE实现中的极性控制方案相关的定时问题。 可能需要用于实现极性控制方案的复用被并入多路复用中，可能需要将半速率数据转换成DFE的延迟元件中的全速率数据。 时钟信号被提供给用极性信息编码的多路复用器。 使用并入极性控制的时钟发生电路来产生各种时钟信号。
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Patent Agency Ranking
公开(公告)号：US09030244B1
公开(公告)日：2015-05-12
申请号：US14155775
申请日：2014-01-15
Applicant: Altera Corporation
Inventor： Mei Luo , Allen K. Chan , Thungoc M. Tran
IPC: H03K3/017
CPC classification number: H03K3/017 , H03K5/1565
Abstract: An integrated circuit includes a duty cycle detection circuit, a comparator circuit, and a tuning circuit. The duty cycle detection circuit receives a clock signal, such as a system clock signal, and detects the level of duty cycle distortion in the clock signal. The comparator circuit then generates an output based on the level of duty cycle distortion that is detected in the clock signal. The tuning circuit may accordingly adjust the clock signal based on the output generated by the comparator circuit to produce an adjusted clock output signal. As an example, the clock output signal produced by the tuning circuit after the adjustment may have a 50% (or significantly close to 50%) duty cycle.
Abstract translation: 集成电路包括占空比检测电路，比较器电路和调谐电路。 占空比检测电路接收诸如系统时钟信号的时钟信号，并检测时钟信号中占空比失真的电平。 然后，比较器电路基于在时钟信号中检测到的占空比失真电平产生输出。 因此，调谐电路可以基于由比较器电路产生的输出来调整时钟信号，以产生经调整的时钟输出信号。 作为示例，在调整之后由调谐电路产生的时钟输出信号可以具有50％（或显着接近50％）占空比。
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公开(公告)号：US09405865B2
公开(公告)日：2016-08-02
申请号：US14133147
申请日：2013-12-18
Applicant: Altera Corporation
Inventor： Peng Li , Masashi Shimanouchi , Thungoc M. Tran , Sergey Shumarayev
CPC classification number: G06F17/5009 , G06F17/5036 , G06F2217/10
Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.
Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。
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公开(公告)号：US20140107997A1
公开(公告)日：2014-04-17
申请号：US14133147
申请日：2013-12-18
Applicant: Altera Corporation
Inventor： Peng Li , Masashi Shimanouchi , Thungoc M. Tran , Sergey Shumarayev
IPC: G06F17/50
CPC classification number: G06F17/5009 , G06F17/5036 , G06F2217/10
Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.
Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。
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6.发明申请SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS 审中-公开用于可编程逻辑器件集成电路的高速串行数据传输器的串行电路公开(公告)号：US20140009188A1
公开(公告)日：2014-01-09
申请号：US14022639
申请日：2013-09-10
Applicant: Altera Corporation
Inventor： Toan Thanh Nguyen , Thungoc M. Tran , Sergey Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong H. Lee
IPC: H03K19/00
CPC classification number: H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。
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7.发明授权Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits 有权用于可编程逻辑器件集成电路上的高速串行数据发射器的串行器电路公开(公告)号：US09077330B2
公开(公告)日：2015-07-07
申请号：US14022639
申请日：2013-09-10
Applicant: Altera Corporation
Inventor： Toan Thanh Nguyen , Thungoc M. Tran , Sergey Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong H. Lee
CPC classification number: H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。
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