公开(公告)号：US10911164B2

公开(公告)日：2021-02-02

申请号：US16140292

申请日：2018-09-24

Applicant: Altera Corporation

Inventor： Neville Carvalho ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC: H04B17/21 ,  H04B17/11 ,  G01R35/00 ,  G12B13/00

Abstract: The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is 10 configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

公开(公告)号：US08995599B1

公开(公告)日：2015-03-31

申请号：US13969427

申请日：2013-08-16

Applicant: Altera Corporation

Inventor： Tien Duc Pham ,  Leon Zheng ,  Sergey Shumarayev ,  Zhi Y. Wong ,  Paul B. Ekas

IPC: H03D3/24 ,  H03L7/08

CPC classification number: H03L7/0802 ,  H03L7/1976 ,  H04J3/047 ,  H04J3/062

Abstract: A phase-locked loop circuit includes phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals. An oscillator circuit causes a frequency of a third periodic signal to vary based on the first control signal. A frequency divider circuit divides the frequency of the third periodic signal by a frequency division value to generate a frequency of the second periodic signal. A delta sigma modulator circuit controls the frequency division value based on second control signals. First storage circuits store the second control signals based on third control signals in response to a fourth periodic signal. A second storage circuit stores an output signal based on a fourth control signal. The fourth periodic signal is generated based on the output signal of the second storage circuit.

Abstract translation: 锁相环电路包括基于第一和第二周期信号之间的相位比较产生第一控制信号的相位检测电路。 振荡器电路使得第三周期信号的频率基于第一控制信号而变化。 分频器电路将第三周期信号的频率除以分频值，以产生第二周期信号的频率。 ΔΣ调制器电路基于第二控制信号控制分频值。 第一存储电路响应于第四周期信号，基于第三控制信号存储第二控制信号。 第二存储电路基于第四控制信号存储输出信号。 基于第二存储电路的输出信号生成第四周期信号。

公开(公告)号：US20190028213A1

公开(公告)日：2019-01-24

申请号：US16140292

申请日：2018-09-24

Applicant: Altera Corporation

Inventor： Neville Carvalho ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC: H04B17/21

Abstract: The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is 10 configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

公开(公告)号：US09025654B1

公开(公告)日：2015-05-05

申请号：US14028071

申请日：2013-09-16

Applicant: Altera Corporation

Inventor： Xiaoyan Su ,  Sriram Narayan ,  Sergey Shumarayev

IPC: H03H7/40 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03038

Abstract: Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.

Abstract translation: 公开了采用均衡技术的系统和方法，其提高均衡器输入灵敏度并降低功耗。 特别地，描述了包括连续时间线性均衡器和判决反馈均衡器的均衡架构，每个具有偏移消除，其使均衡器能够以高数据速率使用。 此外，均衡结构具有旁路判决反馈均衡器的省电模式。 这些偏移消除和省电功能使用可编程器件上的可编程逻辑进行启用和控制。

公开(公告)号：US08866520B1

公开(公告)日：2014-10-21

申请号：US14023174

申请日：2013-09-10

Applicant: Altera Corporation

Inventor： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

IPC: H03L7/06 ,  H04L7/033 ,  H03L7/197

CPC classification number: H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

Abstract: One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及一种可断裂的PLL电路。 断裂PLL电路包括产生第一频率输出的第一锁相环电路，第二锁相环电路; 布置成产生第二频率输出和多个共享输出资源。 可重构电路被布置成使得第一和第二频率输出中的任一个可由多个共享输出资源中的每一个接收。 另一实施例涉及一种集成电路，其包括多个PMA模块，多个多用途PLL电路和可编程时钟网络。 可编程时钟网络被布置为允许由多用途PLL电路输出的时钟信号被PMA模块选择性地用于收发器应用或由用于非收发器应用的其它电路。 还公开了其它实施例和特征。

公开(公告)号：US08798127B2

公开(公告)日：2014-08-05

申请号：US13678163

申请日：2012-11-15

Applicant: Altera Corporation

Inventor： Weiqi Ding ,  Wei Li ,  Sergey Shumarayev

IPC: H03H7/40 ,  H04L27/01 ,  H04L25/03

CPC classification number: H04L25/0274 ,  H04L25/03885 ,  H04L25/14

Abstract: Disclosed are apparatus and methods for adaptive receiver delay equalization. One embodiment relates to a method for adaptive receiver delay equalization. Filtered positive and negative polarity signals are generated by a first variable-delay filter and a second variable-delay filter, respectively. A delay difference is determined between the filtered positive and negative polarity signals, and a skew-indication signal is generated based on the delay difference. A delay control signal is generated based on the skew-indication signal, and the delay control signal is sent to at least one of the first and second variable-delay filters. Other embodiments and features are also disclosed.

Abstract translation: 公开了用于自适应接收机延迟均衡的装置和方法。 一个实施例涉及一种用于自适应接收机延迟均衡的方法。 过滤的正极性和负极性信号分别由第一可变延迟滤波器和第二可变延迟滤波器产生。 在滤波的正极性和负极性信号之间确定延迟差，并且基于延迟差产生偏斜指示信号。 基于偏斜指示信号产生延迟控制信号，并且将延迟控制信号发送到第一和第二可变延迟滤波器中的至少一个。 还公开了其它实施例和特征。

公开(公告)号：US08699648B1

公开(公告)日：2014-04-15

申请号：US13774285

申请日：2013-02-22

Applicant: Altera Corporation

Inventor： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC classification number: H04L7/033

Abstract: One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.

Abstract translation: 一个实施例涉及一种用于集成电路中的接收机的偏移抵消的方法。 接收机设置为相位检测器偏移消除模式，以便确定相位检测器的偏移消除设置。 偏移消除设置被应用于相位检测器。 然后将接收机设置为接收器 - 驱动器偏移消除模式，以便确定接收器驱​​动器的偏移消除设置。 该偏移消除设置被应用于接收器驱动器。 另一实施例涉及被配置为执行接收机偏移消除的集成电路。 该集成电路包括被配置为接收差分输入信号的接收器驱动器，包括多个锁存器的相位检测器，校准控制器，电压源以及第一和第二对开关。 还公开了其它实施例，方面和特征。

公开(公告)号：US20140009188A1

公开(公告)日：2014-01-09

申请号：US14022639

申请日：2013-09-10

Applicant: Altera Corporation

Inventor： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong H. Lee

IPC: H03K19/00

CPC classification number: H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US09350530B1

公开(公告)日：2016-05-24

申请号：US14487867

申请日：2014-09-16

Applicant: ALTERA CORPORATION

Inventor： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding

IPC: H03L7/06 ,  H04L7/033

CPC classification number: H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

Abstract: One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Each PMA module includes multiple CDR circuits, receives multiple serial data signals, and outputs data from those signals in parallel form. The programmable clock network allows the reference clock signals to be selectively shared by the PMA modules and the multiple-purpose PLLs. Another embodiment relates to a method of providing clock signals for multiple purposes in an integrated circuit. Clock signals are generated by a plurality of multiple-purpose PLLs and are selectively distributed to PMA modules arranged at a side of the integrated circuit and to logic circuitry arranged in a core section of the integrated circuit. The clock signals are used by circuitry in the PMA modules for supporting a plurality of data communications channels. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及包括多个PMA模块，多个多用途PLL，多个参考时钟信号输入和可编程时钟网络的集成电路。 每个PMA模块包括多个CDR电路，接收多个串行数据信号，并以并行形式从这些信号中输出数据。 可编程时钟网络允许参考时钟信号由PMA模块和多用途PLL选择性共享。 另一实施例涉及在集成电路中为多个目的提供时钟信号的方法。 时钟信号由多个多用途PLL产生，并且选择性地分配到布置在集成电路侧的PMA模块和布置在集成电路的核心部分中的逻辑电路。 时钟信号由PMA模块中的电路用于支持多个数据通信信道。 还公开了其它实施例和特征。

公开(公告)号：US09077330B2

公开(公告)日：2015-07-07

申请号：US14022639

申请日：2013-09-10

Applicant: Altera Corporation

Inventor： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong H. Lee

IPC: H03M9/00 ,  H03K19/00 ,  H03K19/177 ,  H04L7/00 ,  H04L7/033 ,  H04L25/02 ,  H04L1/24

CPC classification number: H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。