公开(公告)号：US09747076B1

公开(公告)日：2017-08-29

申请号：US14561131

申请日：2014-12-04

Applicant: Altera Corporation

Inventor： Haiyun Yang ,  Tianshu Chi

IPC: G06F7/58

CPC classification number: G06F7/584

Abstract: Integrated circuits with pseudo random bit sequence (PRBS) generation circuitry are provided. The PRBS generation circuitry may be configured to support parallel output generation in multiple modes, where the parallel bit width in each mode can be different. The PRBS generation circuitry may include a linear feedback shift register that implements a desired polynomial, one or more XOR tree circuits that produces the parallel output bits, a multiplexer for selectively routing a subset of the parallel output bits back to the input of the shift register, and a gearbox for performing an adjustable bit width conversion. Configured in this way, the PRBS generation circuitry can provide parallel PRBS generation with an adjustable bit width.