公开(公告)号：US12147377B2

公开(公告)日：2024-11-19

申请号：US18299662

申请日：2023-04-12

Applicant: Altera Corporation

Inventor： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

IPC: G06F13/42 ,  G06F5/06 ,  H04L69/14 ,  H04L49/25

Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

公开(公告)号：US20230289319A1

公开(公告)日：2023-09-14

申请号：US18299662

申请日：2023-04-12

Applicant: Altera Corporation

Inventor： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

IPC: G06F13/42 ,  H04L69/14 ,  G06F5/06

CPC classification number: G06F13/4286 ,  H04L69/14 ,  G06F5/065 ,  H04L49/25

Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

公开(公告)号：US11669479B2

公开(公告)日：2023-06-06

申请号：US17711860

申请日：2022-04-01

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  David W. Mendel

IPC: G06F13/40 ,  G06F13/42 ,  G06F5/06

CPC classification number: G06F13/4022 ,  G06F5/065 ,  G06F13/4018 ,  G06F13/4291 ,  G06F2205/067

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

公开(公告)号：US20210109882A1

公开(公告)日：2021-04-15

申请号：US17131474

申请日：2020-12-22

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  David W. Mendel

IPC: G06F13/40 ,  G06F5/06 ,  G06F13/42

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

公开(公告)号：US20180034748A1

公开(公告)日：2018-02-01

申请号：US15676402

申请日：2017-08-14

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  Vinson Chan ,  Divya Vijayaraghavan ,  Curt Wortman

IPC: H04L12/861 ,  H04L12/863

CPC classification number: H04L49/90 ,  H04L47/6245

Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

公开(公告)号：US10936531B2

公开(公告)日：2021-03-02

申请号：US16792507

申请日：2020-02-17

Applicant: Altera Corporation

Inventor： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

IPC: G06F13/42 ,  H04L29/06 ,  G06F5/06 ,  H04L12/947

Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

公开(公告)号：US20200183877A1

公开(公告)日：2020-06-11

申请号：US16792507

申请日：2020-02-17

Applicant: Altera Corporation

Inventor： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

IPC: G06F13/42 ,  G06F5/06 ,  H04L29/06

Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

公开(公告)号：US10404627B2

公开(公告)日：2019-09-03

申请号：US15676402

申请日：2017-08-14

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  Vinson Chan ,  Divya Vijayaraghavan ,  Curt Wortman

IPC: H04L12/861 ,  H04L12/863

Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

公开(公告)号：US10394737B1

公开(公告)日：2019-08-27

申请号：US14975270

申请日：2015-12-18

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  David W. Mendel

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42 ,  G06F5/06

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1x mode or 2x mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

公开(公告)号：US10348311B2

公开(公告)日：2019-07-09

申请号：US15256377

申请日：2016-09-02

Applicant: Altera Corporation

Inventor： Curt Wortman ,  Keith Duwel ,  Michael Menghui Zheng

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  H03L7/08 ,  G06F1/3234 ,  G06F1/3296 ,  G06F11/07 ,  H03K19/00 ,  H03K19/173 ,  H03K19/177 ,  H04B17/309

Abstract: An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.