公开(公告)号：US10811080B2

公开(公告)日：2020-10-20

申请号：US16215275

申请日：2018-12-10

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: H04L7/00 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  G06F12/02 ,  G11C11/406 ,  G11C21/00 ,  G06F3/06 ,  G11C11/4072 ,  G11C11/4093 ,  H01L27/11582

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US10296479B1

公开(公告)日：2019-05-21

申请号：US14975370

申请日：2015-12-18

Applicant: ALTERA CORPORATION

Inventor： Gregg William Baeckler ,  David W. Mendel

IPC: G06F9/00 ,  G06F13/40 ,  G06F13/38 ,  G11C7/10 ,  G11C19/00 ,  G11C21/00 ,  G06F9/30

Abstract: The present disclosure provides an innovative circuit structure for control insertion into a multiple-word wide data stream. The control-insertion circuit structure is advantageously scalable as the data width increases. An exemplary implementation of the control-insertion circuit structure includes a multiple-layer shifting circuit. The multiple-layer shifting circuit has some similarities with a barrel shifter. However, unlike a barrel shifter, the multiple-layer shifting circuit moves data words in both directions and moves portions of the data to create spaces or holes in the data (rather than moving the entire width as a barrel shifter does). The output of the multiple-layer shifting circuit is a “swiss-cheese-like” structure of data, where the spaces or holes in the data are available for control insertion. Other features, aspects and embodiments are also disclosed.

公开(公告)号：US10192609B2

公开(公告)日：2019-01-29

申请号：US15633677

申请日：2017-06-26

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  G06F12/02 ,  G11C11/406 ,  G11C21/00 ,  G06F3/06 ,  G11C11/4072 ,  G11C11/4093 ,  H04L7/00

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US10126947B2

公开(公告)日：2018-11-13

申请号：US15413732

申请日：2017-01-24

Applicant: Micron Technology, Inc.

Inventor： John D. Leidel

IPC: G06F13/00 ,  G06F3/06 ,  G06F13/42 ,  G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C21/00

Abstract: System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.

公开(公告)号：US09405070B1

公开(公告)日：2016-08-02

申请号：US14713284

申请日：2015-05-15

Applicant: Alcatel-Lucent USA Inc.

Inventor： Guilhem de Valicourt ,  Carlo Ferrari

IPC: G02B6/28 ,  G02B6/12 ,  H01S3/067 ,  G02F1/01 ,  G11C21/00

CPC classification number: G02B6/2861 ,  G02B6/12004 ,  G11C13/04 ,  G11C21/00 ,  H01S3/06754 ,  H01S5/0625 ,  H01S5/1007 ,  H01S5/101 ,  H01S5/5027

Abstract: We disclose an optical buffer having a plurality of optical ports. In some embodiments, an optical signal to be stored may be injected into the buffer through any one of the optical ports and then may be ejected from the buffer, after being stored therein for a selectable amount of time, through any one of the optical ports as well. This feature advantageously enables the optical buffer to also function as an optical switch or router. In an example embodiment, the optical buffer comprises two optical recirculation loops, each of which can store the optical signal by causing it to circulate therein. The buffer is configured to compensate optical losses incurred by the optical signal during this circulation by transferring the optical signal from one loop to the other through an optical amplifier. Due to the latter feature, the optical buffer may be able to store an optical signal, with an acceptable OSNR, for a significantly longer time than certain conventional optical buffers.

Abstract translation: 我们公开了具有多个光学端口的光学缓冲器。 在一些实施例中，要存储的光信号可以通过任何一个光端口注入到缓冲器中，然后可以通过任何一个光端口在缓冲器中存储可选择的时间量之后从缓冲器中弹出 以及。 该特征有利地使得光学缓冲器也可以用作光学交换机或路由器。 在一个示例性实施例中，光学缓冲器包括两个光学循环回路，每个循环回路可以通过使其在其中循环而存储光学信号。 缓冲器被配置为通过光学放大器将光信号从一个环路传送到另一个环路来补偿在该循环期间由光信号引起的光学损耗。 由于后一个特征，光学缓冲器可能能够存储具有可接受的OSNR的光信号比特定的常规光学缓冲器显着更长的时间。

公开(公告)号：US20160070535A1

公开(公告)日：2016-03-10

申请号：US14786080

申请日：2014-06-13

Applicant: TRAVELPORT, LP

Inventor： Bryan Karr

IPC: G06F5/14 ,  G06F13/16 ,  G11C21/00

CPC classification number: G06F5/14 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/544 ,  G06F13/1673 ,  G06F2205/063 ,  G11C21/00

Abstract: Systems and methods of queuing data for multiple readers and writers are provided. Enqueuing operations are disclosed that can process write functionality and can determine whether ring buffers have potentially filled, and dynamically declare a new ring buffer at a multiple of capacity of the current ring. Dequeuing operations are disclosed that can process read functionality for advancing control and determining whether and when to free ring buffers from memory.

Abstract translation: 提供了为多个读取器和写入器排队数据的系统和方法。 公开了能够处理写入功能并且可以确定环形缓冲器是否可能被填充的入队操作，并且以当前环的容量的倍数动态地声明新的环形缓冲器。 公开了可以处理用于前进控制的读取功能并确定是否以及何时从存储器释放环形缓冲器的排队操作。

公开(公告)号：US09099194B2

公开(公告)日：2015-08-04

申请号：US13967245

申请日：2013-08-14

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: H04L25/00 ,  G11C11/406 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  G06F12/02 ,  G11C21/00 ,  H04L7/00

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Abstract translation: 存储器组件包括包含动态随机存取存储器（DRAM）存储单元的存储器核心和用于接收外部命令的第一电路。 外部命令包括指定发送从存储器核心访问的数据的读取命令。 存储器组件还包括响应于读取命令和在校准期间可操作以提供至少第一数据模式和第二数据模式的读取命令和模式寄存器电路将数据发送到外部总线的第二电路。 在校准期间，第一数据模式和第二数据模式中的所选择的一个被响应于在校准期间接收到的读命令，被第二电路发送到外部总线上。 此外，响应于在校准期间接收到的写入命令，第一和第二数据模式中的至少一个被写入模式寄存器电路。

公开(公告)号：US08976579B2

公开(公告)日：2015-03-10

申请号：US13757981

申请日：2013-02-04

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hideaki Fukuzawa ,  Yoshiaki Fukuzumi ,  Hirofumi Morise ,  Akira Kikitsu

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/14 ,  G11C19/08 ,  G11C21/00

CPC classification number: G11C11/161 ,  G11C11/14 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808 ,  G11C21/00

Abstract: According to one embodiment, a magnetic memory element includes: a magnetic wire, a stress application unit, and a recording/reproducing unit. The magnetic wire includes a plurality of domain walls and a plurality of magnetic domains separated by the domain walls. The magnetic wire is a closed loop. The stress application unit is configured to cause the domain walls to circle around along the closed loop a plurality of times by applying stress to the magnetic wire. The recording/reproducing unit is configured to write memory information by changing magnetizations of the circling magnetic domains as the domain walls circle around and to read the written memory information by detecting the magnetizations of the circling magnetic domains.

Abstract translation: 根据一个实施例，磁存储元件包括：磁线，应力施加单元和记录/再现单元。 磁线包括多个畴壁和由畴壁隔开的多个磁畴。 磁线是闭环。 应力施加单元被配置为通过向磁线施加应力使畴壁沿着闭合环多圈。 记录/再现单元被配置为通过随着畴壁围绕而改变环绕磁畴的磁化来写入存储器信息，并且通过检测循环磁畴的磁化来读取写入的存储器信息。

公开(公告)号：US08595573B2

公开(公告)日：2013-11-26

申请号：US13405309

申请日：2012-02-26

Applicant: Ofir Shalvi ,  Naftali Sommer ,  Oren Golov

Inventor： Ofir Shalvi ,  Naftali Sommer ,  Oren Golov

IPC: G11C21/00

CPC classification number: G06F11/181 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/25 ,  H03M13/296

Abstract: A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells.

Abstract translation: 一种用于在包括以块为单位布置的多个存储单元的存储器中的数据存储的方法，包括将第一和第二页存储在存储器的给定块内的存储单元的相应第一和第二组中。 在第一组中识别出一个或多个有缺陷的存储器单元的相应位置的图案。 通过将第一组中识别的模式应用到第二组存储器单元来恢复第二页。

公开(公告)号：US07870454B2

公开(公告)日：2011-01-11

申请号：US12126452

申请日：2008-05-23

Applicant: Kevin W. Gorman ,  Emory D. Keller ,  Michael R. Ouellette ,  Donald L. Wheater

Inventor： Kevin W. Gorman ,  Emory D. Keller ,  Michael R. Ouellette ,  Donald L. Wheater

IPC: G01R31/28 ,  G11C21/00

CPC classification number: G11C29/40 ,  G01R31/31703 ,  G01R31/31704 ,  G11C2029/3202

Abstract: A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.

Abstract translation: 公开了一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法的设计结构。 特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。 测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。 通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器 将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。