公开(公告)号：US09558143B2

公开(公告)日：2017-01-31

申请号：US14273867

申请日：2014-05-09

Applicant: Micron Technology, Inc.

Inventor： John D. Leidel

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/16 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/1621 ,  G06F13/1657 ,  G06F13/1673 ,  G06F13/1684 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/4234 ,  G06F2212/205 ,  G11C7/1075 ,  G11C21/00

Abstract: System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.

Abstract translation: 片上系统（SoC）设备包括用于传送本地存储器分组和系统互连分组的两个分组化存储器总线。 在数据处理系统的原位配置中，两个或更多个SoC与一个或多个混合存储立方体（HMC）耦合。 存储器分组使得能够与给定SoC的存储器域中的本地HMC进行通信。 系统互连分组使得SoC之间的通信和存储器域之间的通信成为可能。 在专用路由配置中，系统中的每个SoC都有自己的内存域来寻址本地HMC和单独​​的系统互连域，以解决连接在系统互连域中的HMC集线器，HMC存储设备或其他SoC设备。

公开(公告)号：US20160286289A1

公开(公告)日：2016-09-29

申请号：US14669503

申请日：2015-03-26

Applicant: Amazon Technologies, Inc.

Inventor： Jason Michael Long ,  Pragyana K. Mishra

IPC: H04Q11/00 ,  H04B10/275

CPC classification number: H04Q11/0062 ,  G11C13/048 ,  G11C21/00 ,  H04B10/275 ,  H04J14/0283 ,  H04Q11/0001 ,  H04Q11/0005 ,  H04Q2011/002 ,  H04Q2011/0083 ,  H04Q2011/0092

Abstract: Optical networks may store information or data therein by maintaining the information or data in motion. The optical networks may include optical fiber rings configured to receive optical signals comprising the information or data and to circulate the optical signals within the optical fiber rings. The optical signals and the information or data may be transferred out of the optical fiber rings in order to amplify the optical signals (e.g., to overcome losses due to attenuation within the optical fiber rings), to analyze the optical signals according to one or more processing techniques, or to transfer the information or data to another computer device upon request. If continued storage of the information or data is required, an optical signal including the information or data may be transferred back into the optical fiber rings and may continue to circulate therein.

Abstract translation: 光网络可以通过维持信息或数据运动来存储信息或数据。 光网络可以包括被配置为接收包括信息或数据的光信号并且在光纤环内循环光信号的光纤环。 可以将光信号和信息或数据从光纤环传送出去，以便放大光信号（例如，克服光纤环内的衰减造成的损耗），以根据一个或多个 处理技术，或者根据要求将信息或数据传送到另一计算机设备。 如果需要继续存储信息或数据，则包括信息或数据的光学信号可以被传送回光纤环并且可以继续在其中循环。

公开(公告)号：US09405070B1

公开(公告)日：2016-08-02

申请号：US14713284

申请日：2015-05-15

Applicant: Alcatel-Lucent USA Inc.

Inventor： Guilhem de Valicourt ,  Carlo Ferrari

IPC: G02B6/28 ,  G02B6/12 ,  H01S3/067 ,  G02F1/01 ,  G11C21/00

CPC classification number: G02B6/2861 ,  G02B6/12004 ,  G11C13/04 ,  G11C21/00 ,  H01S3/06754 ,  H01S5/0625 ,  H01S5/1007 ,  H01S5/101 ,  H01S5/5027

Abstract: We disclose an optical buffer having a plurality of optical ports. In some embodiments, an optical signal to be stored may be injected into the buffer through any one of the optical ports and then may be ejected from the buffer, after being stored therein for a selectable amount of time, through any one of the optical ports as well. This feature advantageously enables the optical buffer to also function as an optical switch or router. In an example embodiment, the optical buffer comprises two optical recirculation loops, each of which can store the optical signal by causing it to circulate therein. The buffer is configured to compensate optical losses incurred by the optical signal during this circulation by transferring the optical signal from one loop to the other through an optical amplifier. Due to the latter feature, the optical buffer may be able to store an optical signal, with an acceptable OSNR, for a significantly longer time than certain conventional optical buffers.

Abstract translation: 我们公开了具有多个光学端口的光学缓冲器。 在一些实施例中，要存储的光信号可以通过任何一个光端口注入到缓冲器中，然后可以通过任何一个光端口在缓冲器中存储可选择的时间量之后从缓冲器中弹出 以及。 该特征有利地使得光学缓冲器也可以用作光学交换机或路由器。 在一个示例性实施例中，光学缓冲器包括两个光学循环回路，每个循环回路可以通过使其在其中循环而存储光学信号。 缓冲器被配置为通过光学放大器将光信号从一个环路传送到另一个环路来补偿在该循环期间由光信号引起的光学损耗。 由于后一个特征，光学缓冲器可能能够存储具有可接受的OSNR的光信号比特定的常规光学缓冲器显着更长的时间。

公开(公告)号：US20160070535A1

公开(公告)日：2016-03-10

申请号：US14786080

申请日：2014-06-13

Applicant: TRAVELPORT, LP

Inventor： Bryan Karr

IPC: G06F5/14 ,  G06F13/16 ,  G11C21/00

CPC classification number: G06F5/14 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/544 ,  G06F13/1673 ,  G06F2205/063 ,  G11C21/00

Abstract: Systems and methods of queuing data for multiple readers and writers are provided. Enqueuing operations are disclosed that can process write functionality and can determine whether ring buffers have potentially filled, and dynamically declare a new ring buffer at a multiple of capacity of the current ring. Dequeuing operations are disclosed that can process read functionality for advancing control and determining whether and when to free ring buffers from memory.

Abstract translation: 提供了为多个读取器和写入器排队数据的系统和方法。 公开了能够处理写入功能并且可以确定环形缓冲器是否可能被填充的入队操作，并且以当前环的容量的倍数动态地声明新的环形缓冲器。 公开了可以处理用于前进控制的读取功能并确定是否以及何时从存储器释放环形缓冲器的排队操作。

公开(公告)号：US09099194B2

公开(公告)日：2015-08-04

申请号：US13967245

申请日：2013-08-14

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: H04L25/00 ,  G11C11/406 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  G06F12/02 ,  G11C21/00 ,  H04L7/00

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Abstract translation: 存储器组件包括包含动态随机存取存储器（DRAM）存储单元的存储器核心和用于接收外部命令的第一电路。 外部命令包括指定发送从存储器核心访问的数据的读取命令。 存储器组件还包括响应于读取命令和在校准期间可操作以提供至少第一数据模式和第二数据模式的读取命令和模式寄存器电路将数据发送到外部总线的第二电路。 在校准期间，第一数据模式和第二数据模式中的所选择的一个被响应于在校准期间接收到的读命令，被第二电路发送到外部总线上。 此外，响应于在校准期间接收到的写入命令，第一和第二数据模式中的至少一个被写入模式寄存器电路。

公开(公告)号：US08976579B2

公开(公告)日：2015-03-10

申请号：US13757981

申请日：2013-02-04

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hideaki Fukuzawa ,  Yoshiaki Fukuzumi ,  Hirofumi Morise ,  Akira Kikitsu

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/14 ,  G11C19/08 ,  G11C21/00

CPC classification number: G11C11/161 ,  G11C11/14 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808 ,  G11C21/00

Abstract: According to one embodiment, a magnetic memory element includes: a magnetic wire, a stress application unit, and a recording/reproducing unit. The magnetic wire includes a plurality of domain walls and a plurality of magnetic domains separated by the domain walls. The magnetic wire is a closed loop. The stress application unit is configured to cause the domain walls to circle around along the closed loop a plurality of times by applying stress to the magnetic wire. The recording/reproducing unit is configured to write memory information by changing magnetizations of the circling magnetic domains as the domain walls circle around and to read the written memory information by detecting the magnetizations of the circling magnetic domains.

Abstract translation: 根据一个实施例，磁存储元件包括：磁线，应力施加单元和记录/再现单元。 磁线包括多个畴壁和由畴壁隔开的多个磁畴。 磁线是闭环。 应力施加单元被配置为通过向磁线施加应力使畴壁沿着闭合环多圈。 记录/再现单元被配置为通过随着畴壁围绕而改变环绕磁畴的磁化来写入存储器信息，并且通过检测循环磁畴的磁化来读取写入的存储器信息。

公开(公告)号：US08699888B2

公开(公告)日：2014-04-15

申请号：US13041968

申请日：2011-03-07

Applicant: Mirco Scaffardi ,  Gianluca Berrettini ,  Antonella Bogoni

Inventor： Mirco Scaffardi ,  Gianluca Berrettini ,  Antonella Bogoni

IPC: H04B10/299 ,  G02F3/00

CPC classification number: G06E1/02 ,  G11C13/04 ,  G11C19/00 ,  G11C21/00

Abstract: An optical linear feedback circuit has an optical loop delay path (10) for recirculating a sequence of optical signals, and an output path for outputting delayed optical signals after circulating one or more times around the loop. A selector (50) is provided for selecting one or more of the delayed optical signals from the sequence, and an optical logic circuit (20) is coupled to carry out a logical operation on the selected delayed optical signals to create an optical feedback signal which is coupled to the optical loop delay path, so that the optical feedback signal can be added to the sequence of optical signals already circulating. By recirculating around a loop, each round trip can be regarded as equivalent to a shift of a shift register, so longer sequences can be built up without needing an additional storage cell for each shift function.

Abstract translation: 光学线性反馈电路具有用于再循环光信号序列的光环路延迟路径（10），以及用于在环路循环一次或多次之后输出延迟光信号的输出路径。 选择器（50）被提供用于从该序列中选择一个或多个延迟的光信号，并且光学逻辑电路（20）被耦合以对所选择的延迟光信号执行逻辑运算以产生光反馈信号， 耦合到光环路延迟路径，使得光反馈信号可以被添加到已经循环的光信号序列中。 通过循环循环，每次往返可被认为等同于移位寄存器的移位，因此可以建立更长的序列，而不需要每个移位函数的附加存储单元。

公开(公告)号：US20130286756A1

公开(公告)日：2013-10-31

申请号：US13460514

申请日：2012-04-30

Applicant: Ted A. Hadley

Inventor： Ted A. Hadley

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/24 ,  G11C19/00 ,  G11C19/28 ,  G11C21/00

Abstract: A memory circuit may include a shift register ring including single-bit shift registers. The circuit may include a clock connected to the shift registers to shift bits within the shift register ring, and a counter connected to the clock and indicating positions of the bits in the shift register ring.

Abstract translation: 存储器电路可以包括包括单位移位寄存器的移位寄存器环。 电路可以包括连接到移位寄存器以移位移位寄存器环中的位的时钟，以及连接到时钟的计数器，并指示移位寄存器环中的位的位置。

公开(公告)号：US20130132314A1

公开(公告)日：2013-05-23

申请号：US13813128

申请日：2010-10-13

Applicant: Gregory Stuart Snider

Inventor： Gregory Stuart Snider

IPC: G06N3/02

CPC classification number: G06N3/02 ,  G06N3/063 ,  G06N3/0635 ,  G11C7/062 ,  G11C7/067 ,  G11C7/1006 ,  G11C11/1673 ,  G11C11/54 ,  G11C13/004 ,  G11C19/00 ,  G11C21/00 ,  G11C27/005 ,  G11C2013/0057

Abstract: Methods and system for modeling the behavior of binary synapses are provided. In one aspect, a method of modeling synaptic behavior includes receiving an analog input signal and transforming the analog input signal into an N-bit codeword, wherein each bit of the N-bit codeword is represented by an electronic pulse (1001). The method includes loading the N-bit codeword into a circular shift register (1002) and sending each bit of the N-bit codeword through one of N switches. Each switch applies a corresponding weight to the bit to produce a weighted bit. A signal corresponding to a summation of the weighted bits is output and represents a synaptic transfer function characterization of a binary synapse (1009).

Abstract translation: 提供了二进制突触行为建模方法和系统。 一方面，一种突触行为建模方法包括接收模拟输入信号并将模拟输入信号变换为N位码字，其中N位码字的每个位由电子脉冲（1001）表示。 该方法包括将N位代码字加载到循环移位寄存器（1002）中，并通过N个开关之一发送N位码字的每个位。 每个开关对该位应用相应的权重以产生加权位。 输出与加权比特的加法相对应的信号，并表示二进制突触的突触传递函数表征（1009）。

公开(公告)号：US20130058160A1

公开(公告)日：2013-03-07

申请号：US13562650

申请日：2012-07-31

Applicant: Joo-Young Hwang

Inventor： Joo-Young Hwang

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C21/00

Abstract: A phase change memory device includes a memory cell array, a register unit and a control unit. The memory cell array includes a plurality of phase change memory cells. The register unit includes a circular queue. The control unit receives a write address and a write data in a write mode, programs the write data in a phase change memory cell corresponding to the write address among the plurality of phase change memory cells, provides the write address and the write data to the register unit, and outputs a write complete signal before a phase of the phase change memory cell is stabilized or after the phase of the phase change memory cell is stabilized based on a logic level of a first result signal received from the register unit. The phase change memory device increases a programming speed.

Abstract translation: 相变存储器件包括存储单元阵列，寄存器单元和控制单元。 存储单元阵列包括多个相变存储单元。 寄存器单元包括一个循环队列。 控制单元以写入模式接收写入地址和写入数据，对与多个相变存储单元中的写入地址相对应的相变存储单元中的写入数据进行编程，将写入地址和写入数据提供给 并且在相变存储单元的相位稳定之前或者在基于从寄存器单元接收到的第一结果信号的逻辑电平使相变存储单元的相位稳定之后输出写入完成信号。 相变存储器件增加编程速度。