公开(公告)号：US11520659B2

公开(公告)日：2022-12-06

申请号：US16741017

申请日：2020-01-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Patrick James Meaney ,  Glenn David Gilda ,  David D. Cadigan ,  Christian Jacobi ,  Lawrence Jones ,  Stephen J. Powell

IPC: G06F11/10 ,  G06F11/07 ,  G11C29/42 ,  G06F9/30 ,  G11C11/406 ,  G06F11/30

Abstract: A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.

公开(公告)号：US20230393999A1

公开(公告)日：2023-12-07

申请号：US17804904

申请日：2022-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Rajat Rao ,  Patrick James Meaney ,  Glenn David Gilda ,  Michael Jason Cade ,  Robert J Sonnelitter, III ,  Hubert Harrer ,  Xiaomin Duan ,  Christian Jacobi ,  Arthur O'Neill

IPC: G06F15/80 ,  G06F13/36

CPC classification number: G06F15/8038 ,  G06F13/36

Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

公开(公告)号：US20230098514A1

公开(公告)日：2023-03-30

申请号：US17484393

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Patrick James Meaney ,  Ashutosh Mishra ,  Paul Allen Ganfield ,  Christian Jacobi ,  Logan Ian Friedman ,  Jentje Leenstra ,  Glenn David Gilda ,  Jason Andrew Thompson ,  Yvonne Hanson Kleppel

IPC: H04L7/00

Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.

公开(公告)号：US11609817B2

公开(公告)日：2023-03-21

申请号：US17470100

申请日：2021-09-09

Applicant: International Business Machines Corporation

Inventor： Patrick James Meaney ,  Glenn David Gilda ,  David D. Cadigan ,  Lawrence Jones

IPC: G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00 ,  G06F11/10 ,  G06F11/07 ,  G06F12/0862 ,  G11C29/42 ,  G11C11/406 ,  G06F13/16

Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.

公开(公告)号：US11200119B2

公开(公告)日：2021-12-14

申请号：US16741008

申请日：2020-01-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Patrick James Meaney ,  Glenn David Gilda ,  David D. Cadigan ,  Lawrence Jones

IPC: G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00 ,  G06F11/10 ,  G06F11/07 ,  G06F12/0862 ,  G11C29/42 ,  G11C11/406 ,  G06F13/16

Abstract: A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.

公开(公告)号：US11960426B2

公开(公告)日：2024-04-16

申请号：US17804904

申请日：2022-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Rajat Rao ,  Patrick James Meaney ,  Glenn David Gilda ,  Michael Jason Cade ,  Robert J Sonnelitter, III ,  Hubert Harrer ,  Xiaomin Duan ,  Christian Jacobi ,  Arthur O'Neill

IPC: G06F13/36

CPC classification number: G06F13/36

Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

公开(公告)号：US11646861B2

公开(公告)日：2023-05-09

申请号：US17484393

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Patrick James Meaney ,  Ashutosh Mishra ,  Paul Allen Ganfield ,  Christian Jacobi ,  Logan Ian Friedman ,  Jentje Leenstra ,  Glenn David Gilda ,  Jason Andrew Thompson ,  Yvonne Hanson Kleppel

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  H04L7/0079 ,  H04L7/0095

Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.

公开(公告)号：US11449397B2

公开(公告)日：2022-09-20

申请号：US16567308

申请日：2019-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gregory J. Fredeman ,  Glenn David Gilda ,  Thomas E. Miller ,  Arthur O'Neill

IPC: G06F11/00 ,  G06F11/20 ,  G06F12/0875 ,  G06F11/16 ,  G11C29/30 ,  G06F11/10 ,  G11C29/04

Abstract: A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.

公开(公告)号：US20210073087A1

公开(公告)日：2021-03-11

申请号：US16567308

申请日：2019-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gregory J. FREDEMAN ,  Glenn David Gilda ,  Thomas E. Miller ,  Arthur O'Neill

IPC: G06F11/20 ,  G06F12/0875 ,  G06F11/16 ,  G06F11/10 ,  G11C29/30

Abstract: A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.

公开(公告)号：US20240103967A1

公开(公告)日：2024-03-28

申请号：US17954464

申请日：2022-09-28

Applicant: International Business Machines Corporation

Inventor： Barry M. Trager ,  Patrick James Meaney ,  Glenn David Gilda ,  Lawrence Jones

IPC: G06F11/10 ,  G06F11/22

CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F11/2273

Abstract: A memory controller stores each of a plurality of data blocks encoded by error correction code (ECC) across multiple channels of a redundant memory system. Based on receiving, from the memory system, channel data of a fetch operation requesting a data block, the memory controller decodes the channel data and concurrently generates a predicted channel mark based on tests of channel-induced syndromes generated from the channel data. The predicted channel mark identifies a marked channel among the multiple channels as a likely source of data errors. The memory controller determines whether the decoding detects an uncorrectable error in the channel data and, based on determining the decoding detects an uncorrectable error in the channel data, re-reads channel data corresponding to the data block and corrects the re-read channel data by excluding, from decoding, channel data received from the marked channel.