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    Single-ended low-swing power-savings mechanism with process compensation
    1.
    发明授权
    Single-ended low-swing power-savings mechanism with process compensation 有权
    具有过程补偿功能的单端低功耗节能机构

    公开(公告)号：US09047930B2

    公开(公告)日：2015-06-02

    申请号：US13951801

    申请日：2013-07-26

    Applicant: International Business Machines Corporation

    Inventor： Gregory J. Fredeman ,  Abraham Mathews ,  Donald W. Plass ,  Vinod Ramadurai

    IPC: G11C7/00 ,  G11C7/12

    CPC classification number: G11C7/12 ,  G11C5/148 ,  G11C2207/2227

    Abstract: A single-ended low-swing power-savings mechanism is provided. The mechanism comprises a precharge device that turns off in an evaluation phase and a first biasing device is always on. Within the mechanism, a strength of a keeper device is changed to a first level in response to an input of the second biasing device being at a first voltage level. Within the mechanism the strength of the keeper device is changed to a second level in response to the input of the second biasing device being at a second voltage level. Responsive to receiving a (precharged voltage level read data line signal, a precharged voltage level of the first node falls faster when the keeper device is weakened to a first level. The keeper device turns on in response to receiving a LOW signal and pulls up the voltage at the first node so that a HIGH signal is output.

    Abstract translation: 提供单端低功耗节能机制。 该机构包括在评估阶段中关闭并且第一偏置装置总是打开的预充电装置。 在机构内，响应于第二偏置装置的输入处于第一电压电平，保持装置的强度被改变到第一电平。 在机构内，响应于第二偏置装置的输入处于第二电压电平，保持装置的强度被改变到第二电平。 响应于接收（预充电电压电平读取数据线信号），当保持器件被削弱到第一电平时，第一节点的预充电电压电平下降得更快，保持器装置响应于接收到低电平信号而导通， 电压，从而输出高电平信号。

    DYNAMIC CASCODE-MANAGED HIGH-VOLTAGE WORD-LINE DRIVER CIRCUIT
    3.
    发明申请
    DYNAMIC CASCODE-MANAGED HIGH-VOLTAGE WORD-LINE DRIVER CIRCUIT 有权
    动态CASCODE管理的高压字线驱动电路

    公开(公告)号：US20150162059A1

    公开(公告)日：2015-06-11

    申请号：US14300617

    申请日：2014-06-10

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Gregory J. Fredeman ,  Abraham Mathews ,  Donald W. Plass ,  Kenneth J. Reyer

    IPC: G11C7/12

    CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1069 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4096 ,  G11C2029/1202

    Abstract: A method of operation of a high-voltage word-line driver circuit for a memory device prevents any single transistor of the driver from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.

    Abstract translation: 一种用于存储器件的高电压字线驱动电路的操作方法防止驱动器的任何单个晶体管具有产生字线输出信号的全部电源电压而不被施加于任何单个晶体管 的字线驱动电路。 一对共射共基器件与输入级的下拉器件和输入级的上拉器件串联连接，并且使用参考电压进行偏置以控制当下拉器件上的最大压降 下拉装置关闭，并且上拉装置处于活动状态，并且当下拉装置处于活动状态时，控制上拉装置上的最大压降。 输出级还包括保护输出下拉和上拉器件的共源共栅器件，偏置输入和输出共源共栅对的参考电压可能是相同的参考电压。

    Negative voltage generation for computer memory
    5.
    发明授权
    Negative voltage generation for computer memory 有权

    公开(公告)号：US10832756B1

    公开(公告)日：2020-11-10

    申请号：US16587501

    申请日：2019-09-30

    Applicant: International Business Machines Corporation

    Inventor： Gregory J. Fredeman ,  Thomas E. Miller ,  Dinesh Kannambadi ,  Phil Paone ,  Donald W. Plass

    IPC: G11C5/14 ,  G11C11/4074 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4076

    Abstract: Techniques for negative voltage generation for a computer memory are described herein. An aspect includes enabling a first negative word line voltage (VWL) clock generator. Another aspect includes providing, by the first VWL clock generator, based on a clock signal, a first pump clock signal to a first VWL pump, and a second pump clock signal to a second VWL pump. Another aspect includes generating a VWL based on the first VWL pump and the second VWL pump, wherein the VWL is provided to a word line driver of a computer memory module. Another aspect includes comparing the VWL to a VWL reference voltage. Another aspect includes, based on the VWL being below the VWL reference voltage, disabling the first VWL clock generator, wherein the first VWL pump and the second VWL pump are disabled based on disabling the first VWL clock generator.

    DYNAMIC HIGH VOLTAGE DRIVER WITH ADJUSTABLE CLAMPED OUTPUT LEVEL
    7.
    发明申请
    DYNAMIC HIGH VOLTAGE DRIVER WITH ADJUSTABLE CLAMPED OUTPUT LEVEL 有权
    具有可调节钳位输出电平的动态高电压驱动器

    公开(公告)号：US20160352336A1

    公开(公告)日：2016-12-01

    申请号：US15052644

    申请日：2016-02-24

    Applicant: International Business Machines Corporation

    Inventor： Gregory J. Fredeman ,  Abraham Mathews ,  Donald W. Plass ,  Kenneth J. Reyer

    IPC: H03K19/0185 ,  H03K5/08

    CPC classification number: H03K19/018521 ,  H03K5/08

    Abstract: A driver circuit and associated techniques include managing voltage driving an electronic device. An input signal having a first voltage level is received. Processes may perform level shifting of the first voltage level to a second voltage level. The second voltage level may be clamped, for instance, but a diode circuit. The second output voltage level may be programmable, as may be current and resistance levels of the driver circuit.

    Abstract translation: 驱动器电路和相关技术包括管理驱动电子设备的电压。 接收具有第一电压电平的输入信号。 处理可以执行第一电压电平的电平移位到第二电压电平。 第二电压电平可以被钳位，例如二极管电路。 第二输出电压电平可以是可编程的，可以是驱动器电路的电流和电阻电平。

    Single-Ended Low-Swing Power-Savings Mechanism with Process Compensation
    8.
    发明申请
    Single-Ended Low-Swing Power-Savings Mechanism with Process Compensation 有权
    具有过程补偿功能的单端低回转节能机制

    公开(公告)号：US20150029803A1

    公开(公告)日：2015-01-29

    申请号：US13951801

    申请日：2013-07-26

    Applicant: International Business Machines Corporation

    Inventor： Gregory J. Fredeman ,  Abraham Mathews ,  Donald W. Plass ,  Vinod Ramadurai

    IPC: G11C7/12

    CPC classification number: G11C7/12 ,  G11C5/148 ,  G11C2207/2227

    Abstract: A single-ended low-swing power-savings mechanism is provided. The mechanism comprises a precharge device that turns off in an evaluation phase and a first biasing device is always on. Within the mechanism, a strength of a keeper device is changed to a first level in response to an input of the second biasing device being at a first voltage level. Within the mechanism the strength of the keeper device is changed to a second level in response to the input of the second biasing device being at a second voltage level. Responsive to receiving a (precharged voltage level read data line signal, a precharged voltage level of the first node falls faster when the keeper device is weakened to a first level. The keeper device turns on in response to receiving a LOW signal and pulls up the voltage at the first node so that a HIGH signal is output.

    Abstract translation: 提供单端低功耗节能机制。 该机构包括在评估阶段中关闭并且第一偏置装置总是打开的预充电装置。 在机构内，响应于第二偏置装置的输入处于第一电压电平，保持装置的强度被改变到第一电平。 在机构内，响应于第二偏置装置的输入处于第二电压电平，保持装置的强度被改变到第二电平。 响应于接收（预充电电压电平读取数据线信号），当保持器件被削弱到第一电平时，第一节点的预充电电压电平下降得更快，保持器装置响应于接收到低电平信号而导通， 电压，从而输出高电平信号。

    Testing multi-port array in integrated circuits
    9.
    发明授权
    Testing multi-port array in integrated circuits 有权

    公开(公告)号：US11069422B1

    公开(公告)日：2021-07-20

    申请号：US16922115

    申请日：2020-07-07

    Applicant: International Business Machines Corporation

    Inventor： Matthew Steven Hyde ,  Uma Srinivasan ,  Thomas J. Knips ,  Gregory J. Fredeman

    IPC: G11C29/44 ,  G11C29/46 ,  G11C29/34 ,  G11C29/26 ,  G11C29/14

    Abstract: A method for testing a circuit includes performing, by a test engine, a test of a memory element of the circuit, the test accesses a memory location in the memory element, the memory location is identified by an address, and the memory location is accessed via a first port associated with a first port select bit. The method further includes, in response to detecting a failure associated with the memory location, determining an existing entry for the address in a failed address register, and determining that the existing entry in the failed address register is associated with a second port select bit, distinct from the first port select bit. The method further includes, in response to the second port select bit being distinct from the first port select bit, setting a multi-port failure flag for the memory element that is being tested.

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