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公开(公告)号：US11520659B2
公开(公告)日：2022-12-06
申请号：US16741017
申请日：2020-01-13
发明人： Patrick James Meaney , Glenn David Gilda , David D. Cadigan , Christian Jacobi , Lawrence Jones , Stephen J. Powell
摘要： A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.
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公开(公告)号：US20230393999A1
公开(公告)日：2023-12-07
申请号：US17804904
申请日：2022-06-01
发明人： Rajat Rao , Patrick James Meaney , Glenn David Gilda , Michael Jason Cade , Robert J Sonnelitter, III , Hubert Harrer , Xiaomin Duan , Christian Jacobi , Arthur O'Neill
CPC分类号： G06F15/8038 , G06F13/36
摘要： Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.
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3.发明公开公开(公告)号：US20240103967A1
公开(公告)日：2024-03-28
申请号：US17954464
申请日：2022-09-28
CPC分类号： G06F11/1068 , G06F11/1004 , G06F11/2273
摘要： A memory controller stores each of a plurality of data blocks encoded by error correction code (ECC) across multiple channels of a redundant memory system. Based on receiving, from the memory system, channel data of a fetch operation requesting a data block, the memory controller decodes the channel data and concurrently generates a predicted channel mark based on tests of channel-induced syndromes generated from the channel data. The predicted channel mark identifies a marked channel among the multiple channels as a likely source of data errors. The memory controller determines whether the decoding detects an uncorrectable error in the channel data and, based on determining the decoding detects an uncorrectable error in the channel data, re-reads channel data corresponding to the data block and corrects the re-read channel data by excluding, from decoding, channel data received from the marked channel.
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公开(公告)号：US11907074B2
公开(公告)日：2024-02-20
申请号：US17484415
申请日：2021-09-24
发明人： Patrick James Meaney , Ashutosh Mishra , Paul Allen Ganfield , Christian Jacobi , Logan Ian Friedman , Jentje Leenstra , Glenn David Gilda , Michael B. Spear
CPC分类号： G06F11/1423 , G06F5/06 , G06F11/0745 , G06F13/28 , G06F13/385
摘要： Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.
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公开(公告)号：US20230115533A1
公开(公告)日：2023-04-13
申请号：US17484415
申请日：2021-09-24
发明人： Patrick James Meaney , Ashutosh Mishra , Paul Allen Ganfield , Christian Jacobi , Logan Ian Friedman , Jentje Leenstra , Glenn David Gilda , Michael B. Spear
摘要： Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.
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公开(公告)号：US20240311260A1
公开(公告)日：2024-09-19
申请号：US18182598
申请日：2023-03-13
发明人： Rajat Rao , Patrick James Meaney , Ashutosh Mishra , Jason Andrew Thompson , Nandini Gaadam Nagaraj
CPC分类号： G06F11/187 , G06F11/165
摘要： A computer system, computer readable storage medium, and computer-implemented method for dynamically degrading a link between multiple processing devices to facilitate uninterrupted service between the multiple processing devices. The method includes determining a number of undegraded lanes within the link. The method also includes determining, subject to the number of undegraded lanes, a first operational degrade mode for the link. The method further includes initiating a retrain of the link to a second operational degrade mode. The method also includes dynamically, subject to the first degrade mode of operation, determining one or more message packet types to transmit through the link during the link retrain, thereby facilitating uninterrupted service between the multiple processing devices.
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公开(公告)号：US11960426B2
公开(公告)日：2024-04-16
申请号：US17804904
申请日：2022-06-01
发明人： Rajat Rao , Patrick James Meaney , Glenn David Gilda , Michael Jason Cade , Robert J Sonnelitter, III , Hubert Harrer , Xiaomin Duan , Christian Jacobi , Arthur O'Neill
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.
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8.发明授权公开(公告)号：US11646861B2
公开(公告)日：2023-05-09
申请号：US17484393
申请日：2021-09-24
发明人： Patrick James Meaney , Ashutosh Mishra , Paul Allen Ganfield , Christian Jacobi , Logan Ian Friedman , Jentje Leenstra , Glenn David Gilda , Jason Andrew Thompson , Yvonne Hanson Kleppel
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H04L7/0079 , H04L7/0095
摘要： A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.
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9.发明申请公开(公告)号：US20230098514A1
公开(公告)日：2023-03-30
申请号：US17484393
申请日：2021-09-24
发明人： Patrick James Meaney , Ashutosh Mishra , Paul Allen Ganfield , Christian Jacobi , Logan Ian Friedman , Jentje Leenstra , Glenn David Gilda , Jason Andrew Thompson , Yvonne Hanson Kleppel
IPC分类号： H04L7/00
摘要： A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.
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公开(公告)号：US11609817B2
公开(公告)日：2023-03-21
申请号：US17470100
申请日：2021-09-09
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00 , G06F11/10 , G06F11/07 , G06F12/0862 , G11C29/42 , G11C11/406 , G06F13/16
摘要： A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.
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