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公开(公告)号：US20150253808A1
公开(公告)日：2015-09-10
申请号：US14280782
申请日：2014-05-19
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.
摘要翻译： 公开了一种电子系统，其可以包括相位流水线，数据流水线，输入相位选择器和输出相位选择器。 相位流水线可以具有由时钟信号计时的锁存器，并被设计成将相位信号从相位输入传播到相位输出。 数据流水线可以具有由相位流水线时钟信号定时的锁存器，并被设计为将数据从数据输入传播到数据输出。 输入相位选择器可以被设计为响应于相位输入处的数据，向数据输入端提供来自数据输入端的数据的反相或非反相副本到数据流水线数据输入端。 输出相位选择器可以被设计为响应于相位流水线输出值，将来自数据流水线输出的数据的反相或非反相副本提供给输出相位选择器数据输出。
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公开(公告)号：US09250645B2
公开(公告)日：2016-02-02
申请号：US14198790
申请日：2014-03-06
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.
摘要翻译： 公开了一种电子系统，其可以包括相位流水线，数据流水线，输入相位选择器和输出相位选择器。 相位流水线可以具有由时钟信号计时的锁存器，并被设计成将相位信号从相位输入传播到相位输出。 数据流水线可以具有由相位流水线时钟信号定时的锁存器，并被设计为将数据从数据输入传播到数据输出。 输入相位选择器可以被设计为响应于相位输入处的数据，向数据输入端提供来自数据输入端的数据的反相或非反相副本到数据流水线数据输入端。 输出相位选择器可以被设计为响应于相位流水线输出值，将来自数据流水线输出的数据的反相或非反相副本提供给输出相位选择器数据输出。
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公开(公告)号：US09057766B2
公开(公告)日：2015-06-16
申请号：US13689044
申请日：2012-11-29
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3187
CPC分类号： G01R31/318566 , G01R31/318569 , G01R31/3187
摘要： A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out.
摘要翻译： 提供了用于识别集成电路器件内的故障锁存器的机构。 在与识别的故障多输入签名寄存器相关联的一组扫描链上启动测试序列。 对于测试序列中的一组测试部分中的每个测试部分，在多输入签名寄存器的输出和一组期望值中的对应值之间执行比较。 响应于确定匹配，计数器的值增加。 响应于不匹配，停止计数器的递增，并且读出提供集成电路装置中的故障锁存器指示的计数器的值。
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公开(公告)号：US09383767B2
公开(公告)日：2016-07-05
申请号：US14280782
申请日：2014-05-19
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.
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公开(公告)号：US20150253807A1
公开(公告)日：2015-09-10
申请号：US14198790
申请日：2014-03-06
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.
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公开(公告)号：US09128150B2
公开(公告)日：2015-09-08
申请号：US14060175
申请日：2013-10-22
发明人： Michael W. Harper , Mack W. Riley
IPC分类号： G01R31/28 , G11C29/00 , G06F11/00 , G01R31/3177 , G01R31/3185 , G01R31/3187 , G01R31/317 , G06F11/25 , G06F11/27 , G06F11/30 , G06F11/34 , G11C29/12
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/2856 , G01R31/317 , G01R31/31724 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318566 , G01R31/318586 , G01R31/3187 , G06F11/25 , G06F11/27 , G06F11/3003 , G06F11/3065 , G06F11/3089 , G06F11/3466 , G11C29/12
摘要： An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.
摘要翻译： 集成电路包括LBIST控制器，其操作用于在集成电路的核心逻辑的至少一个选择上运行测试程序，以测试核心逻辑的至少一个选择的可操作性。 该集成电路还包括一个监控逻辑结构，可操作以从由LBIST控制器激活的至少一个特定控制信号中检测对于测试程序执行的至少一种类型的操作，用于控制核心逻辑的至少一个选择以执行测试程序 从至少一个用于控制核心逻辑的至少一个选择的操作的控制信号中。
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公开(公告)号：US08943458B1
公开(公告)日：2015-01-27
申请号：US14027594
申请日：2013-09-16
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
IPC分类号： G06F17/50
CPC分类号： G06F11/2236 , G06F11/263 , G11C29/06
摘要： Various embodiments include approaches for determining burn-in workload conditions for an integrated circuit (IC) design. Some embodiments include burn-in testing the IC design using the workload conditions. In some embodiments, a computer implemented method includes obtaining survey data about at least one application workload for an integrated circuit (IC) corresponding to an IC design; generating latch state and clocking statistics about the IC design for the at least one application workload based upon the survey data; and determining a set of burn-in workload conditions for the IC design based upon the latch state and clocking statistics about the IC design.
摘要翻译： 各种实施例包括用于确定集成电路（IC）设计的老化工作负载条件的方法。 一些实施例包括使用工作负载条件对IC设计进行老化测试。 在一些实施例中，计算机实现的方法包括获得关于与IC设计相对应的集成电路（IC）的至少一个应用工作负载的调查数据; 基于所述调查数据产生关于所述至少一个应用工作负载的IC设计的锁存状态和时钟统计; 以及基于关于IC设计的锁存状态和时钟统计来确定用于IC设计的一组老化工作负载条件。
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公开(公告)号：US20140149814A1
公开(公告)日：2014-05-29
申请号：US13689044
申请日：2012-11-29
IPC分类号： G01R31/3177
CPC分类号： G01R31/318566 , G01R31/318569 , G01R31/3187
摘要： A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out.
摘要翻译： 提供了用于识别集成电路器件内的故障锁存器的机构。 在与识别的故障多输入签名寄存器相关联的一组扫描链上启动测试序列。 对于测试序列中的一组测试部分中的每个测试部分，在多输入签名寄存器的输出和一组期望值中的对应值之间执行比较。 响应于确定匹配，计数器的值增加。 响应于不匹配，停止计数器的递增，并且读出提供集成电路装置中的故障锁存器指示的计数器的值。
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公开(公告)号：US20140053035A1
公开(公告)日：2014-02-20
申请号：US14060175
申请日：2013-10-22
发明人： Michael W. Harper , Mack W. Riley
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/2856 , G01R31/317 , G01R31/31724 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318566 , G01R31/318586 , G01R31/3187 , G06F11/25 , G06F11/27 , G06F11/3003 , G06F11/3065 , G06F11/3089 , G06F11/3466 , G11C29/12
摘要： An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.
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公开(公告)号：US10608763B2
公开(公告)日：2020-03-31
申请号：US15988869
申请日：2018-05-24
摘要： Method and apparatus for packeted analysis, comprising: testing a phase rotator at a plurality of phase rotator positions, by propagating a first series of bits of a first pattern through a channel of an integrated circuit; propagating a second series of bits of a second pattern through the channel; measuring, for the given phase rotator position, a value of each bit propagated through the channel; and in response to determining that measured values of the bits propagated through the channel conform to one of the first pattern and the second pattern, indicating that the given phase rotator position satisfies an accuracy threshold; determining a sequence of phase rotator positions of the plurality of phase rotator positions in which the accuracy threshold is satisfied; and in response to determining that the sequence of phase rotator positions does not satisfy an eye width threshold, failing the channel of the integrated circuit.
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