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    TEST DECOMPRESSOR AND TEST METHOD THEREOF
    1.
    发明申请
    TEST DECOMPRESSOR AND TEST METHOD THEREOF 审中-公开

    公开(公告)号：US20180120378A1

    公开(公告)日：2018-05-03

    申请号：US15479580

    申请日：2017-04-05

    Applicant: NATIONAL CHENG KUNG UNIVERSITY

    Inventor： KUEN-JONG LEE ,  JHEN-ZONG CHEN

    IPC: G01R31/3185 ,  G01R31/28 ,  G06F11/25

    CPC classification number: G01R31/318533 ,  G01R31/2851 ,  G01R31/31937 ,  G06F11/25

    Abstract: A test decompressor and a test method thereof for converting original input data of one single test input into test vectors for testing a circuit under test (CUT) containing scan chains are revealed. The test decompressor includes a test data spreader, a test configuration switch, and a test controller. The test data spreader converts the original input data into a plurality of test data. The test configuration switch receives the original input data and the plurality of test data and transfers these data to scan chains of the CUT. The test controller receives the original input data and outputs a select signal to the test configuration switch for switching current test configuration to another test configuration. The scan chains in the CUT are divided into several scan groups and the scan chains in each scan group share the same test data. Thus the test data volume can be significantly reduced.

    Remote testing
    4.
    发明授权
    Remote testing 有权
    远程测试

    公开(公告)号：US09547584B2

    公开(公告)日：2017-01-17

    申请号：US13413832

    申请日：2012-03-07

    Applicant: Anish Acharya ,  Jeson Patel

    Inventor： Anish Acharya ,  Jeson Patel

    IPC: G06F11/36 ,  G06F11/25 ,  G06F11/22 ,  G06F11/26 ,  G06Q10/06

    CPC classification number: G06F11/3688 ,  G06F11/22 ,  G06F11/25 ,  G06F11/26 ,  G06Q10/0639

    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for remote testing. In one aspect, a method includes receiving a first message from a first user device indicating initialization of a client application. The method includes determining that the first user device is a member of a first testing group. The method includes identifying a first testing component associated with the first testing group and capable of altering the client application. The method includes sending the first testing component to the first user device.

    Abstract translation: 方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于远程测试。 一方面，一种方法包括从第一用户设备接收指示客户端应用的初始化的第一消息。 该方法包括确定第一用户设备是第一测试组的成员。 该方法包括识别与第一测试组相关联并且能够改变客户端应用的第一测试组件。 该方法包括将第一测试组件发送到第一用户设备。

    Cell library and method for designing an asynchronous integrated circuit
    6.
    发明授权
    Cell library and method for designing an asynchronous integrated circuit 有权
    用于设计异步集成电路的单元库和方法

    公开(公告)号：US09430600B2

    公开(公告)日：2016-08-30

    申请号：US14395344

    申请日：2013-04-22

    Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives

    Inventor： Yvain Thonnart ,  Pascal Vivet

    IPC: G06F17/50 ,  G06F1/10 ,  G06F11/25 ,  G06F13/40 ,  G06F1/12

    CPC classification number: G06F17/505 ,  G06F1/10 ,  G06F1/12 ,  G06F11/25 ,  G06F13/4009 ,  G06F17/5045 ,  G06F17/5059 ,  G06F2217/84 ,  Y02D10/14 ,  Y02D10/151

    Abstract: An asynchronous integrated circuit is designed from a library of cells comprising at least one cell having parameters of signal propagation between a first terminal and a second terminal and between the second terminal and a third terminal depending on the parameter of signal propagation between the first and the third terminal. A synchronous integrated circuit corresponding to the asynchronous integrated circuit is synthesized using said cell to represent a portion of the asynchronous circuit, said cell being rated by a dummy clock signal. The synthesized integrated circuit is verified using the parameter of signal propagation between the first terminal and the third terminal to simulate the operation of said portion of the asynchronous circuit.

    Abstract translation: 从包括至少一个具有在第一终端和第二终端之间的信号传播参数以及第二终端和第三终端之间的参数的至少一个小区的小区库设计异步集成电路，这取决于第一和第二终端之间的信号传播参数 第三码头。 使用所述单元来合成对应于异步集成电路的同步集成电路，以表示异步电路的一部分，所述单元被虚拟时钟信号额定。 使用第一端子和第三端子之间的信号传播参数来验证合成集成电路，以模拟异步电路的所述部分的操作。

    Delayed authentication debug policy
    7.
    发明授权
    Delayed authentication debug policy 有权
    延迟认证调试策略

    公开(公告)号：US09430347B2

    公开(公告)日：2016-08-30

    申请号：US14580588

    申请日：2014-12-23

    Applicant: Michael Neve De Mevergnies ,  Hermann W. Gartler ,  Michael S. Bair

    Inventor： Michael Neve De Mevergnies ,  Hermann W. Gartler ,  Michael S. Bair

    IPC: H04L29/06 ,  G06F11/25 ,  G06F11/27

    CPC classification number: G01R31/31719 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/00 ,  G06F11/25 ,  G06F11/27

    Abstract: A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.

    Abstract translation: 诸如处理器或片上系统（SoC）的底盘平台包括实现包括策略生成器的调试机箱安全系统的逻辑，以控制来自测试访问端口的访问。 策略生成器可以将调试策略分发到在本地强制调试策略的至少一个逻辑块。 调试策略可以包括延迟的认证策略，其中分发调试资产，并且机箱平台最初被锁定以防止经由测试访问端口的调试访问。 经验证的调试用户可以稍后解锁机箱平台，以启用调试操作。 调试策略还可以包括实时执行策略和即时调试策略。

    System and method for error logging
    9.
    发明授权
    System and method for error logging 有权
    错误记录的系统和方法

    公开(公告)号：US09389940B2

    公开(公告)日：2016-07-12

    申请号：US13780248

    申请日：2013-02-28

    Applicant: Silicon Graphics International Corp.

    Inventor： Mark Larson ,  Michael Brown ,  Gary Meyer

    IPC: G06F11/00 ,  G06F11/07

    CPC classification number: G06F11/0772 ,  G06F11/0724 ,  G06F11/25

    Abstract: Error data is read from error registers and written into a buffer. A computing node uses a BIOS to read the error data, rearm the error register and write the data into a memory mapped buffer. A hub chip supports creation of a shared memory system of computing nodes. A management controller in the computing node extracts error data from the buffer. The error data preferably consists essentially of the error register identifiers and the contents of the error registers. A system management node receives the error data from the management controllers in the computing nodes. The system management node may be coupled to but separate from the computing nodes.

    Abstract translation: 错误数据从错误寄存器中读取并写入缓冲区。 计算节点使用BIOS读取错误数据，重新设置错误寄存器并将数据写入存储器映射缓冲区。 集线器芯片支持创建计算节点的共享存储器系统。 计算节点中的管理控制器从缓冲器中提取错误数据。 错误数据优选地基本上由错误寄存器标识符和错误寄存器的内容组成。 系统管理节点从计算节点中的管理控制器接收错误数据。 系统管理节点可以耦合到但是与计算节点分离。

    TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS
    10.
    发明申请
    TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS 有权
    用便携式场景模型和不同级别测试SOC

    公开(公告)号：US20150302126A1

    公开(公告)日：2015-10-22

    申请号：US14689596

    申请日：2015-04-17

    Applicant: Breker Verification Systems

    Inventor： Adnan Hamid ,  Kairong Qian ,  Kieu Do

    IPC: G06F17/50

    CPC classification number: G01R31/3177 ,  G01R31/31813 ,  G06F3/0484 ,  G06F9/4881 ,  G06F11/2205 ,  G06F11/25 ,  G06F11/263 ,  G06F11/3688 ,  G06F17/5009 ,  G06F17/5027 ,  G06F17/5068 ,  G06T11/206

    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

    Abstract translation: 描述了一种用于测试片上系统（SoC）的方法。 该方法包括解析文件以确定要执行SoC的组件的功能。 所述方法还包括接收所述SoC的所需输出并且基于所述SoC的期望输出生成测试场景模型。 测试场景模型包括功能的多个模块表示，并且包括两个模块表示之间的一个或多个连接。 所需的输出作为测试场景模型的性能约束。 测试场景模型还包括基于期望输出，模块表示和一个或多个连接生成的SoC的输入。 测试场景模型包括从输入通过模块表示的路径和到期望输出的连接。

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