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    TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS
    4.
    发明申请
    TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS 有权
    用便携式场景模型和不同级别测试SOC

    公开(公告)号：US20150302126A1

    公开(公告)日：2015-10-22

    申请号：US14689596

    申请日：2015-04-17

    Applicant: Breker Verification Systems

    Inventor： Adnan Hamid ,  Kairong Qian ,  Kieu Do

    IPC: G06F17/50

    CPC classification number: G01R31/3177 ,  G01R31/31813 ,  G06F3/0484 ,  G06F9/4881 ,  G06F11/2205 ,  G06F11/25 ,  G06F11/263 ,  G06F11/3688 ,  G06F17/5009 ,  G06F17/5027 ,  G06F17/5068 ,  G06T11/206

    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

    Abstract translation: 描述了一种用于测试片上系统（SoC）的方法。 该方法包括解析文件以确定要执行SoC的组件的功能。 所述方法还包括接收所述SoC的所需输出并且基于所述SoC的期望输出生成测试场景模型。 测试场景模型包括功能的多个模块表示，并且包括两个模块表示之间的一个或多个连接。 所需的输出作为测试场景模型的性能约束。 测试场景模型还包括基于期望输出，模块表示和一个或多个连接生成的SoC的输入。 测试场景模型包括从输入通过模块表示的路径和到期望输出的连接。

    TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS
    5.
    发明申请
    TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS 审中-公开

    公开(公告)号：US20190391204A1

    公开(公告)日：2019-12-26

    申请号：US16553083

    申请日：2019-08-27

    Applicant: Breker Verification Systems

    Inventor： Adnan Hamid ,  Kairong Qian ,  Kieu Do ,  Joerg Grosse

    IPC: G01R31/3177 ,  G01R31/3181 ,  G06F17/50 ,  G06F3/0484 ,  G06F11/36 ,  G06F11/22 ,  G06F11/263 ,  G06T11/20 ,  G06F9/48 ,  G06F11/25

    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

    Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models
    9.
    发明授权
    Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models 有权
    计划在不同的计算机线程内执行的场景模型以及与场景模型一起使用的内存区域的调度

    公开(公告)号：US09316689B2

    公开(公告)日：2016-04-19

    申请号：US14689649

    申请日：2015-04-17

    Applicant: Breker Verification Systems

    Inventor： Adnan Hamid ,  Kairong Qian ,  Kieu Do ,  Joerg Grosse

    IPC: G06F17/50 ,  G01R31/3177 ,  G06F3/0484 ,  G06F11/36

    CPC classification number: G01R31/3177 ,  G01R31/31813 ,  G06F3/0484 ,  G06F9/4881 ,  G06F11/2205 ,  G06F11/25 ,  G06F11/263 ,  G06F11/3688 ,  G06F17/5009 ,  G06F17/5027 ,  G06F17/5068 ,  G06T11/206

    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

    Abstract translation: 描述了一种用于测试片上系统（SoC）的方法。 该方法包括解析文件以确定要执行SoC的组件的功能。 所述方法还包括接收所述SoC的所需输出并且基于所述SoC的期望输出生成测试场景模型。 测试场景模型包括功能的多个模块表示，并且包括两个模块表示之间的一个或多个连接。 所需的输出作为测试场景模型的性能约束。 测试场景模型还包括基于期望输出，模块表示和一个或多个连接生成的SoC的输入。 测试场景模型包括从输入通过模块表示的路径和到期望输出的连接。

    SCHEDULING OF SCENARIO MODELS FOR EXECUTION WITHIN DIFFERENT COMPUTER THREADS AND SCHEDULING OF MEMORY REGIONS FOR USE WITH THE SCENARIO MODELS
    10.
    发明申请
    SCHEDULING OF SCENARIO MODELS FOR EXECUTION WITHIN DIFFERENT COMPUTER THREADS AND SCHEDULING OF MEMORY REGIONS FOR USE WITH THE SCENARIO MODELS 有权
    在不同的计算机线程中执行场景模型的调度和使用场景模型的存储器区域的调度

    公开(公告)号：US20150301108A1

    公开(公告)日：2015-10-22

    申请号：US14689649

    申请日：2015-04-17

    Applicant: Breker Verification Systems

    Inventor： Adnan Hamid ,  Kairong Qian ,  Kieu Do

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/31813 ,  G06F3/0484 ,  G06F9/4881 ,  G06F11/2205 ,  G06F11/25 ,  G06F11/263 ,  G06F11/3688 ,  G06F17/5009 ,  G06F17/5027 ,  G06F17/5068 ,  G06T11/206

    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

    Abstract translation: 描述了一种用于测试片上系统（SoC）的方法。 该方法包括解析文件以确定要执行SoC的组件的功能。 所述方法还包括接收所述SoC的所需输出并且基于所述SoC的期望输出生成测试场景模型。 测试场景模型包括功能的多个模块表示，并且包括两个模块表示之间的一个或多个连接。 所需的输出作为测试场景模型的性能约束。 测试场景模型还包括基于期望输出，模块表示和一个或多个连接生成的SoC的输入。 测试场景模型包括从输入通过模块表示的路径和到期望输出的连接。

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