公开(公告)号：US20230168963A1

公开(公告)日：2023-06-01

申请号：US17729145

申请日：2022-04-26

申请人： Fulian Precision Electronics (Tianjin) Co., LTD.

发明人： XIAO-LONG ZHOU ,  MING-HUA YU

IPC分类号： G06F11/07 ,  G06F11/22 ,  G06F11/25 ,  G06F9/50

CPC分类号： G06F11/0793 ,  G06F11/2247 ,  G06F11/25 ,  G06F9/505

摘要： A system for debugging server startups incorporated in a method applied in a server includes voltage regulators, a complex programmable logic device (CPLD), a transmitting device, and a display device. The voltage regulators transmit power-on signals required when the server is started. The CPLD receives the power-on signals, collects a second signal from the power on signals, and converts the second signals into a second data. The transmitting device receives the second data and parses the second data into a third data. The displaying device receives the third data and displays power-on signals that do not meet required standard during startup of server, according to the third data.

公开(公告)号：US10776523B2

公开(公告)日：2020-09-15

申请号：US15933586

申请日：2018-03-23

申请人： Kone Corporation

发明人： Sampo Ahokas ,  Antti Hovi ,  Ferenc Staengler

IPC分类号： G06F21/00 ,  G06F21/73 ,  G06F21/57 ,  G06F11/25 ,  G06F11/273

摘要： The invention refers to a method for accessing an passenger transportation device control means comprising several separated printed circuit boards (PCB), whereby each of these PCBs comprises a unique identifier (ID), and in which method the passenger transportation device control means comprise a matching table which is used by the passenger transportation device control means to perform a matching test to check the identifier of at least two of the PCBs and to put the passenger transportation device control means into normal operation only if their IDs match the IDs of the matching table. A service technician connects via a key to the passenger transportation device control means, which key enables the service technician to set the passenger transportation device control means into a fault finding mode, in which fault finding mode the passenger transportation device control means are initiated to skip the matching test before getting into operation, whereby the fault finding mode is terminated at the latest when the service technician terminates the key-based connection with the passenger transportation device control means.

公开(公告)号：US10482205B2

公开(公告)日：2019-11-19

申请号：US15658086

申请日：2017-07-24

申请人： Xilinx, Inc.

发明人： Akhilesh Mahajan ,  Bokka Abhiram Sai Krishna ,  Keshava Gopal Goud Cheruku

IPC分类号： G06F17/50 ,  G01R31/3177 ,  G06F11/25

摘要： Monitoring signals in an integrated circuit can include monitoring a probed signal of an integrated circuit using a logic analyzer circuit implemented within the integrated circuit, detecting state changes in the probed signal using the logic analyzer circuit, and generating, within the logic analyzer circuit, a file specifying time stamped state changes of the probed signal.

公开(公告)号：US10481990B2

公开(公告)日：2019-11-19

申请号：US15474799

申请日：2017-03-30

申请人： Intel Corporation

发明人： Patrik Eder ,  Rolf H. Kuehnis ,  Enrico D. Carrieri

IPC分类号： G06F11/267 ,  G06F11/25 ,  G01R31/317

摘要： Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.

公开(公告)号：US10429442B2

公开(公告)日：2019-10-01

申请号：US15621995

申请日：2017-06-13

申请人： Breker Verification Systems

发明人： Adnan Hamid ,  Kairong Qian ,  Kieu Do ,  Joerg Grosse

IPC分类号： G06F11/00 ,  G01R31/3177 ,  G01R31/3181 ,  G06F3/0484 ,  G06F11/36 ,  G06F17/50 ,  G06F11/22 ,  G06F11/263 ,  G06T11/20 ,  G06F9/48 ,  G06F11/25

摘要： A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

公开(公告)号：US10365326B2

公开(公告)日：2019-07-30

申请号：US15868940

申请日：2018-01-11

申请人： Breker Verification Systems

发明人： Adnan Hamid ,  Kairong Qian ,  Kieu Do ,  Joerg Grosse

IPC分类号： G01R31/3177 ,  G06F11/263 ,  G06F17/50 ,  G01R31/3181 ,  G06F11/25 ,  G06F9/48 ,  G06F3/0484 ,  G06F11/36 ,  G06F11/22 ,  G06T11/20

摘要： A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two module representations of the plurality of module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the plurality of module representations, and the one or more connections. The test scenario model includes a path from the input via the plurality of module representations and the one or more connections to the desired output.

公开(公告)号：US10354742B2

公开(公告)日：2019-07-16

申请号：US15420720

申请日：2017-01-31

申请人： STMicroelectronics International N.V

发明人： Swapnil Bahl ,  Shray Khullar

IPC分类号： G06F11/25 ,  G11C29/32 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/34

摘要： An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.

公开(公告)号：US10302700B2

公开(公告)日：2019-05-28

申请号：US15473100

申请日：2017-03-29

申请人： STMicroelectronics, Inc.

发明人： Vinay Kumar ,  Pramod Kumar

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/25 ,  G01R31/317 ,  G01R31/3181 ,  G01R31/3183

摘要： Disclosed herein is a test circuit for a device under test. The test circuit includes a test data source and a test data target. A debug chain is coupled between the test data source and test data target, and operates in either a clock debug mode or a test mode. The debug chain, when in the test mode, is deactivated. The debug chain, when in the clock debug mode, receives the test pattern data from the test data source and stores the test pattern data, generates a clock debug signature from the stored test pattern data while clocked by a test clock, and outputs the clock debug signature to the test data target, the clock debug signature indicative of whether the test clock is operating properly.

公开(公告)号：US20190108160A1

公开(公告)日：2019-04-11

申请号：US16086666

申请日：2017-04-13

申请人： Hitachi Automotive Systems, Ltd.

发明人： Satoshi OTSUKA ,  Kohei SAKURAI

IPC分类号： G06F15/78 ,  G06F11/25

摘要： The present invention provides a technology for comprehensive verification of the safety of the design of functions, on the basis of a safety analysis result. The disclosed vehicle control system verification device is equipped with a storage device that stores programs for verifying the safety of the logical architecture of a vehicle control system, and a processor that reads the programs from the storage device and verifies the safety of the logical architecture. On the basis of safety analysis result information that is supplied, the processor executes a process for verifying whether the logical architecture has logical functions corresponding to the safety analysis result.

公开(公告)号：US20190087522A1

公开(公告)日：2019-03-21

申请号：US16134020

申请日：2018-09-18

申请人： Mentor Graphics Corporation

发明人： Khaled Salah Mohamed ,  Hans Erich Multhaup ,  Robert John Bloor

IPC分类号： G06F17/50 ,  G06F11/25 ,  G06F11/26 ,  G11C29/46 ,  G11C29/56

摘要： A hardware model of a memory comprises: first circuitry configured to supply a memory status value for the memory which is changed upon a full-memory erase operation; second circuitry configured to supply a sector status value for each memory sector of the memory which is changed to a value equal to the memory status value when a write operation is performed on the each memory sector of the memory; and third circuitry configured to supply, when a read operation is performed on a memory sector of the memory, a value stored in the memory sector as output of the read operation if the sector status value for the memory sector is equal to the memory status value or a predefined value as the output of the read operation in other situations.