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公开(公告)号：US10546081B2
公开(公告)日：2020-01-28
申请号：US16134020
申请日：2018-09-18
摘要： A hardware model of a memory comprises: first circuitry configured to supply a memory status value for the memory which is changed upon a full-memory erase operation; second circuitry configured to supply a sector status value for each memory sector of the memory which is changed to a value equal to the memory status value when a write operation is performed on the each memory sector of the memory; and third circuitry configured to supply, when a read operation is performed on a memory sector of the memory, a value stored in the memory sector as output of the read operation if the sector status value for the memory sector is equal to the memory status value or a predefined value as the output of the read operation in other situations.
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公开(公告)号：US10678976B2
公开(公告)日：2020-06-09
申请号：US15873879
申请日：2018-01-17
发明人： Mahmoud Mohamed Ali , Mohamed Abdelsalam Ahmed Hassan , Ashraf Mohamed Salem , Robert John Bloor
IPC分类号： G06F30/30 , G06F13/00 , G06F30/331 , G06F40/14
摘要： Aspects of the disclosed technology relate to techniques for protocol analysis during a circuit design verification process. A protocol-specific message capture unit captures messages while or after being transmitted over one or more communication channels between a circuit design model and one or more target devices. A protocol-independent interface unit receives signals carrying the messages and information for processing the messages from the protocol-specific message capture unit. After processing the messages, the protocol-independent interface unit sends the messages to an analysis unit for analyzing the messages based on a protocol file. The analysis unit may then output the messages for displaying.
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公开(公告)号：US20180300440A1
公开(公告)日：2018-10-18
申请号：US15873879
申请日：2018-01-17
发明人： Mahmoud Mohamed Ali , Mohamed Abdelsalam Ahmed Hassan , Ashraf Mohamed Salem , Robert John Bloor
摘要： Aspects of the disclosed technology relate to techniques for protocol analysis during a circuit design verification process. A protocol-specific message capture unit captures messages while or after being transmitted over one or more communication channels between a circuit design model and one or more target devices. A protocol-independent interface unit receives signals carrying the messages and information for processing the messages from the protocol-specific message capture unit. After processing the messages, the protocol-independent interface unit sends the messages to an analysis unit for analyzing the messages based on a protocol file. The analysis unit may then output the messages for displaying.
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公开(公告)号：US11144691B2
公开(公告)日：2021-10-12
申请号：US15594382
申请日：2017-05-12
摘要： Disclosed herein are example embodiments of methods, apparatus, and systems for transactors configured for use in a hardware emulation environment and designed to adapt to speed changes dynamically at runtime in addition to providing dynamic port mapping. Among the embodiments disclosed herein is an emulation system comprising one or more configurable hardware components (e.g., configurable logic blocks) configured to implement a mutable port group transactor in communication with a design under test being emulated by the emulation system. The emulation system can further comprise a host computer in communication with the emulator and configured to provide configuration commands to the emulator that alter the mutable port group transactor from a first configuration to a second configuration.
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公开(公告)号：US20190087522A1
公开(公告)日：2019-03-21
申请号：US16134020
申请日：2018-09-18
摘要： A hardware model of a memory comprises: first circuitry configured to supply a memory status value for the memory which is changed upon a full-memory erase operation; second circuitry configured to supply a sector status value for each memory sector of the memory which is changed to a value equal to the memory status value when a write operation is performed on the each memory sector of the memory; and third circuitry configured to supply, when a read operation is performed on a memory sector of the memory, a value stored in the memory sector as output of the read operation if the sector status value for the memory sector is equal to the memory status value or a predefined value as the output of the read operation in other situations.
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公开(公告)号：US20170351795A1
公开(公告)日：2017-12-07
申请号：US15594382
申请日：2017-05-12
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Disclosed herein are example embodiments of methods, apparatus, and systems for transactors configured for use in a hardware emulation environment and designed to adapt to speed changes dynamically at runtime in addition to providing dynamic port mapping. Among the embodiments disclosed herein is an emulation system comprising one or more configurable hardware components (e.g., configurable logic blocks) configured to implement a mutable port group transactor in communication with a design under test being emulated by the emulation system. The emulation system can further comprise a host computer in communication with the emulator and configured to provide configuration commands to the emulator that alter the mutable port group transactor from a first configuration to a second configuration.
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