公开(公告)号：US11113441B1

公开(公告)日：2021-09-07

申请号：US16911805

申请日：2020-06-25

Applicant: Mentor Graphics Corporation

Inventor： Charles W Selvidge ,  Jean-Marc Brault ,  Jean-Paul Clavequin ,  Laurent Vuillemin

IPC: G06F30/34 ,  H04B1/40 ,  G06F30/343 ,  G06F30/347 ,  G06F119/10 ,  G06F119/02

Abstract: Each reconfigurable hardware modeling circuit of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device comprises: a model computation subsystem configurable either to model elements of a circuit design, or to serve as a testbench element, or both, and a network subsystem comprising: network circuitry and signal reduction circuitry, the signal reduction circuitry configurable to perform a signal reduction function, the signal reduction function combining a plurality of status signals into a single status signal, the plurality of status signals comprising status signals received from one or more reconfigurable hardware modeling circuits in the plurality of reconfigurable hardware modeling circuits. Alternatively or additionally, each network circuit of a plurality of network circuits in the reconfigurable hardware modeling device may comprise signal reduction circuitry configurable to perform the signal reduction function.

公开(公告)号：US20210248299A1

公开(公告)日：2021-08-12

申请号：US16788545

申请日：2020-02-12

Applicant: Mentor Graphics Corporation

Inventor： Vasileios Kourkoulos ,  Lin Du ,  Renbo Chen

IPC: G06F30/398 ,  G06N20/00 ,  G06F30/392

Abstract: This application discloses a computing system implementing a parasitic extraction tool to generate a parasitic model from physical design layout of an integrated circuit. The computing system also can implement a machine-learning classifier that, when trained with a training data set, can classify the physical design layout based on physical or electrical characteristics associated with the physical design layout, and can utilize the classification to select a set of scaling coefficients. The computing system can apply the selected set of the scaling coefficients to adjust coupling capacitances in the parasitic model and generate a parasitic netlist for the physical design layout. The computing system can generate the training data set by determining sets of the scaling coefficients from the test physical design layouts and labeling the test physical design layouts with the sets of the scaling coefficients.

公开(公告)号：US11042181B2

公开(公告)日：2021-06-22

申请号：US16669608

申请日：2019-10-31

Applicant: Mentor Graphics Corporation

Inventor： Jean-Francois Cote

IPC: G06F1/08 ,  G06F13/28 ,  G06F13/40

Abstract: A circuit comprises a burst clock control and gating device configured to generate a modified clock signal in a test mode by allowing a preset number of clock pulses of a clock signal to go through during each clock cycle of a reference clock signal, and a plurality of clock gating devices. Each of the plurality of clock gating devices comprises a multiplexing device, wherein the modified clock signal is coupled to a selector input of the multiplexing device, and input signal generation circuitry configured to ensure the timing of the transitions on the output are derived purely from the timing of the transitions of the clock and not by the timing of the transition of the first and second inputs of the multiplexer.

公开(公告)号：US10984150B2

公开(公告)日：2021-04-20

申请号：US14609880

申请日：2015-01-30

Applicant: Mentor Graphics Corporation

Inventor： Vikas Maddukuri

IPC: G06F30/18 ,  G06F8/71 ,  G06F113/16

Abstract: This application discloses a system implementing tools and mechanisms to identify alterations made to a baseline harness design that describes a wire harness, and selectively modify a target harness design based, at least in part, on the alterations made to the baseline harness design. The tools and mechanisms can perform the selective modification of the target harness design through a three-way comparison of the baseline harness design, an altered version of the baseline harness design, and the target harness design. During the three-way comparison, the tools and mechanisms can compare the target harness design to the baseline harness design, and compare the altered version of the baseline harness design to the baseline harness design. The tools and mechanisms can then selectively modify the target harness design based on the alterations made to the baseline harness design and the differences between the target harness design to the baseline harness design.

公开(公告)号：US10937509B1

公开(公告)日：2021-03-02

申请号：US16553890

申请日：2019-08-28

Applicant: Mentor Graphics Corporation

Inventor： Kwan Him Lam

IPC: G11C16/30 ,  G11C29/02 ,  G11C11/41 ,  G11C5/14 ,  G11C29/50

Abstract: This application discloses a memory device to retain stored data when receiving a voltage supply having at least a retention voltage level. The retention voltage level varies based on a supply voltage and a temperature of an environment around the memory device. A sensitive circuit can adjust the voltage supply received by the memory device based on the supply voltage and the temperature. The sensitive circuit can alter a memory bias supply voltage for the memory device to adjust the voltage supply towards the retention voltage level. The sensitive circuit can include a temperature dependent circuit to generate a bias voltage based on the supply voltage and the temperature, and an adjustment circuit to alter the memory bias supply voltage based on the bias voltage. The adjustment circuit also can include high temperature circuitry to adjust the memory bias supply voltage based on a leakage current from the memory device.

公开(公告)号：US20210033669A1

公开(公告)日：2021-02-04

申请号：US16933359

申请日：2020-07-20

Applicant: Mentor Graphics Corporation

Inventor： Wu-Tung Cheng ,  Szczepan Urban ,  Jakub Janicki ,  Manish Sharma ,  Yu Huang

IPC: G01R31/3177

Abstract: A circuit comprises a scan chain comprising one or more multi-bit flip-flops, a plurality of multiplexers, and new scan enable signal generation circuitry. Each of the plurality of multiplexers is associated with a particular bit of the one or more multi-bit flip-flops with an output of the each of the plurality of multiplexers coupled to a data input of the particular bit, which is configured to select, based on a scan direction control signal, between an input signal from functional circuitry of the circuit and an input signal from a data output of a bit of the scan chain immediately following the particular bit in a normal scan shift direction. The new scan enable signal generation circuitry is configured to generate a new scan enable signal for the one or more multi-bit flip-flops based on the scan direction control signal and a scan enable signal for the scan chain.

公开(公告)号：US20210018563A1

公开(公告)日：2021-01-21

申请号：US16982299

申请日：2019-03-21

Applicant: Mentor Graphics Corporation

Inventor： Janusz Rajski ,  Yu Huang ,  Sylwester Milewski ,  Jerzy Tyszer

IPC: G01R31/3185 ,  G01R31/3181

Abstract: A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.

公开(公告)号：US10895864B2

公开(公告)日：2021-01-19

申请号：US16413686

申请日：2019-05-16

Applicant: Mentor Graphics Corporation

Inventor： Fedor G. Pikus

IPC: G05B19/4097 ,  G03F7/20 ,  G06F111/20 ,  G06F119/18

Abstract: Disclosed systems and methods may support fabric-independent multi-patterning. A system may include a coloring constraint access engine and a fabric-independent multi-patterning engine. The coloring constraint access engine may be configured to access a set of coloring constraints to apply to geometric elements of a circuit design without accessing a fabric layer that defines a layout of the geometric elements of the circuit design, the set of coloring constraints applicable to multi-patterning the geometric elements of the circuit design to support manufacture of circuit layers using multiple manufacturing steps (e.g., via complementary lithographic masks). The fabric-independent multi-patterning engine may be configured to perform, independent of the fabric layer, a pattern coloring process according to the set of coloring constraints to determine a color assignment for the geometric elements, respectively.

公开(公告)号：US10889255B2

公开(公告)日：2021-01-12

申请号：US16472331

申请日：2017-12-20

Applicant: Bayerische Motoren Werke Aktiengesellschaft ,  Mentor Graphics Corporation

Inventor： Daniel Franze ,  Carsten Schmid ,  Georg Spoerlein ,  Reiner Striebel

IPC: B60R16/03 ,  G06F1/30 ,  G06F1/32 ,  G06F9/4401

Abstract: A device for electrical energy management of a vehicle system of a motor vehicle includes a power supply for supplying energy to the vehicle system of the motor vehicle. The power supply has a normal operation mode and a stand-by operation mode. A distributing device has voltage levels on the output side for supplying electrical energy to vehicle system components of the vehicle system. A state-monitoring device monitors the electrical energy supply of the power supply and controls the distributing device. A computer device has an operating system device and a volatile computer data memory that is designed to be kept energized even in the stand-by operation mode of the device for energy management, in such a way that the volatile computer data memory does not lose the data stored therein. A method and a motor vehicle corresponding to the device are also provided.

公开(公告)号：US10796044B2

公开(公告)日：2020-10-06

申请号：US16146749

申请日：2018-09-28

Applicant: Mentor Graphics Corporation

Inventor： Michał Paszek ,  Tomasz Zielski ,  Michał Ferdek ,  Pawel Cieslak ,  Marek Mossakowski

IPC: G06F30/30 ,  G06F30/327 ,  G06F30/392 ,  G06F111/12

Abstract: This application discloses a computing system implementing a schematic capture tool to place and connect parts in a schematic design of a printed circuit board assembly. The computing system implementing the schematic capture tool can select a type of communication interface to connect the parts in the schematic design and identify an interface definition that corresponds to the selected type of communication interface. The schematic capture tool can locate a mapping that describes connectivity between the parts and the interface definition, and automatically modify the schematic design to include an instance of the interface definition in the schematic design and connect the parts in the schematic design to the instance of the interface definition based on the mapping. The schematic capture tool also can utilize the interface definition to set constraints for or add terminations to the connection between the parts in the schematic design.