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    SYSTEM DIRECTED TESTING
    1.
    发明公开
    SYSTEM DIRECTED TESTING 审中-公开

    公开(公告)号：US20240320113A1

    公开(公告)日：2024-09-26

    申请号：US18186466

    申请日：2023-03-20

    Applicant: Future Dial, Inc.

    Inventor： Angel Michelle Anderson ,  Hongshan Zhang

    IPC: G06F11/273 ,  G06F11/22

    CPC classification number: G06F11/2733 ,  G06F11/2294

    Abstract: A method includes selecting a first of a plurality of devices-under-test that has been connected in electronic communication with the test device for a longest period of time compared to others of the plurality of devices-under-test. A first task is performed on the first of the plurality of devices-under-test. After completing the first task, determining whether the test device needs to perform the first task on a second of the plurality of devices-under-test. Causing the first task to be performed on the second of the plurality of devices-under-test or selecting a third of the plurality of devices-under-test that has been connected in electronic communication with the test device for a next longest period of time compared to others of the plurality of devices-under-test.

    Techniques for testing semiconductor devices
    2.
    发明授权
    Techniques for testing semiconductor devices 有权

    公开(公告)号：US12079097B2

    公开(公告)日：2024-09-03

    申请号：US17075628

    申请日：2020-10-20

    Applicant: NVIDIA CORPORATION

    Inventor： Animesh Khare ,  Ashish Kumar ,  Shantanu Sarangi ,  Rahul Garg

    IPC: G06F11/273 ,  G06F11/22 ,  G06F13/28 ,  G06F13/42

    CPC classification number: G06F11/2733 ,  G06F11/2268 ,  G06F13/28 ,  G06F13/4282 ,  G06F2213/0026

    Abstract: Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.

    SOC-ORIENTED CONCURRENT TEST SYSTEM FOR MULTIPLE CLOCK DOMAINS AND TEST METHOD THEREOF
    3.
    发明公开
    SOC-ORIENTED CONCURRENT TEST SYSTEM FOR MULTIPLE CLOCK DOMAINS AND TEST METHOD THEREOF 审中-公开

    公开(公告)号：US20240220381A1

    公开(公告)日：2024-07-04

    申请号：US17801527

    申请日：2022-04-18

    Applicant: Macrotest Semiconductor Inc.

    Inventor： Guoliang Mao ,  Zhijie Bao

    IPC: G06F11/273 ,  G01R31/317

    CPC classification number: G06F11/2733 ,  G01R31/31727

    Abstract: The present disclosure relates to a System On Chip (SOC)-oriented concurrent test system and method for multiple clock domains, and belongs to the technical field of chip detection. A board system of the present disclosure includes a board, and a clock domain controller, a slot bus controller and a test subsystem which are arranged on the board; the clock domain controller is connected to the test subsystem and the slot bus controller; the slot bus controller is connected to a backplane bus; and the test subsystem includes a test processor and a signal processing unit; the test processor includes a test pattern memory, a memory control, a timing generator, a pattern generator and a command generator. In the present disclosure, by means of a concurrent test method for multiple clock domains, the test efficiency of a single SOC is improved, and the test cost of the single chip is also reduced, thus increasing the benefit. A higher coverage rate for detecting a failure of a chip that works in a concurrent working state of multiple modules is achieved, and the yield of chips after encapsulation is increased.

    USB integrated circuit, testing platform and operating method for USB integrated circuit
    4.
    发明授权
    USB integrated circuit, testing platform and operating method for USB integrated circuit 有权

    公开(公告)号：US11914491B2

    公开(公告)日：2024-02-27

    申请号：US17985920

    申请日：2022-11-14

    Applicant: VIA LABS, INC.

    Inventor： Hao-Hsuan Chiu

    IPC: G06F11/22 ,  G01R1/04 ,  G06F11/273

    CPC classification number: G06F11/2273 ,  G01R1/0416 ,  G06F11/221 ,  G06F11/2733 ,  G06F2213/0042

    Abstract: A USB integrated circuit (IC), a testing platform and an operating method for USB integrated circuit are provided. The USB integrated circuit includes a USB port physical layer (PHY) circuit, a first lane adapter, a second lane adapter, a routing circuit, and a USB transport layer circuit. The USB PHY circuit is configured to transmit a differential signal between the USB integrated circuit and an outside device. When the USB integrated circuit operates in a testing mode, the routing circuit electrically connects the first lane adapter to the USB PHY circuit. When the USB integrated circuit operates in a working mode, the routing circuit electrically connects the second lane adapter to the USB PHY circuit. The USB transport layer circuit is coupled to the first lane adapter and the second lane adapter.

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