公开(公告)号：US12044720B1

公开(公告)日：2024-07-23

申请号：US17801529

申请日：2022-04-18

Applicant: Macrotest Semiconductor Inc.

Inventor： Guoliang Mao

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2834

Abstract: The present disclosure discloses a multi-core test processor, and an integrated circuit test system and method. The multi-core test processor includes a co-test-processor-sync-controller, a master-test-processor, two or more co-test-processors, and a test subsystem command switching device. Several co-test-processors are introduced under the master-test-processor. The master-test-processor will deliver test patterns that require concurrent testing to the co-test-processors for execution, so as to complete test items similar to the asynchronous signal match test. After the co-test-processors complete the test, the master-test-processor continues to carry out the subsequent test. The present disclosure can achieve asynchronous concurrent test on multiple sites and improve the test efficiency. Meanwhile, idling of fewer test channels can be avoided when asynchronous test channels are allocated to each site, thereby improving test channel utilization rate.

公开(公告)号：US20240219456A1

公开(公告)日：2024-07-04

申请号：US17801528

申请日：2022-04-18

Applicant: Macrotest Semiconductor Inc.

Inventor： Quanren Li ,  Guoliang Mao

IPC: G01R31/28

CPC classification number: G01R31/2884

Abstract: The present disclosure discloses a mixed signal test device based on graphical control, A Tester-On-board architecture is used to extend a power generation and measurement unit, an analog waveform generation and collection unit and an analog waveform control unit on a digital waveform pattern generation and measurement board. The logic control unit is configured to generate and measure a digital pattern of a System on Chip (SOC) to be tested to achieve generation and collection of the digital waveform, is configured to control the analog waveform control unit to achieve generation and collection control of an analog waveform of the SOC to be tested, and is configured to control the power generation and measurement unit to achieve generation and collection control of power of the SOC to be tested, so that generation and measurement of the digital pattern of the SOC to be tested, generation and collection control of the analog waveform, and generation and collection control of the power are simultaneously concurrently executed. The mixed signal test device based on graphical control is easy and efficient in resource coordination and control.

公开(公告)号：US12130718B2

公开(公告)日：2024-10-29

申请号：US17801527

申请日：2022-04-18

Applicant: Macrotest Semiconductor Inc.

Inventor： Guoliang Mao ,  Zhijie Bao

IPC: G06F11/273 ,  G01R31/317

CPC classification number: G06F11/2733 ,  G01R31/31727

Abstract: The present disclosure relates to a System On Chip (SOC)-oriented concurrent test system and method for multiple clock domains, and belongs to the technical field of chip detection. A board system of the present disclosure includes a board, and a clock domain controller, a slot bus controller and a test subsystem which are arranged on the board; the clock domain controller is connected to the test subsystem and the slot bus controller; the slot bus controller is connected to a backplane bus; and the test subsystem includes a test processor and a signal processing unit; the test processor includes a test pattern memory, a memory control, a timing generator, a pattern generator and a command generator. In the present disclosure, by means of a concurrent test method for multiple clock domains, the test efficiency of a single SOC is improved, and the test cost of the single chip is also reduced, thus increasing the benefit. A higher coverage rate for detecting a failure of a chip that works in a concurrent working state of multiple modules is achieved, and the yield of chips after encapsulation is increased.

公开(公告)号：US12111349B2

公开(公告)日：2024-10-08

申请号：US17801528

申请日：2022-04-18

Applicant: Macrotest Semiconductor Inc.

Inventor： Quanren Li ,  Guoliang Mao

IPC: G01R31/28

CPC classification number: G01R31/2884

Abstract: The present disclosure discloses a mixed signal test device based on graphical control. A Tester-On-board architecture is used to extend a power generation and measurement unit, an analog waveform generation and collection unit and an analog waveform control unit on a digital waveform pattern generation and measurement board. The logic control unit is configured to generate and measure a digital pattern of a System on Chip (SOC) to be tested to achieve generation and collection of the digital waveform, is configured to control the analog waveform control unit to achieve generation and collection control of an analog waveform of the SOC to be tested, and is configured to control the power generation and measurement unit to achieve generation and collection control of power of the SOC to be tested, so that generation and measurement of the digital pattern of the SOC to be tested, generation and collection control of the analog waveform, and generation and collection control of the power are simultaneously concurrently executed. The mixed signal test device based on graphical control is easy and efficient in resource coordination and control.

公开(公告)号：US20240248820A1

公开(公告)日：2024-07-25

申请号：US17801525

申请日：2022-04-18

Applicant: Macrotest Semiconductor Inc.

Inventor： Wanchao Liu ,  Guoliang Mao

IPC: G06F11/22 ,  G06F11/263

CPC classification number: G06F11/2221 ,  G06F11/263

Abstract: The present disclosure discloses an automatic learning method and system for a digital test vector. The system includes an upper computer, a pattern generator PG, a driver DRIVER, a comparator COMPARE and a history random access memory HRAM. The method includes: writing a pattern file, the pattern file including an input pin timing and an output pin timing, wherein the input pin timing is provided by a device under test, and the output pin timing is configured to be in a learning state; running the pattern file, and recording a running state; reading recorded running state data, and acquiring an output pin state, recorded within certain time, in the running state data; and correcting the output pin timing in the running pattern file according to the acquired output pin state to obtain a corrected output timing, thus obtaining a corrected pattern file. The present disclosure greatly improves the development efficiency, reduces writing of the characteristic of an output pin of a chip, and lowers the writing difficulty.

公开(公告)号：US12061529B1

公开(公告)日：2024-08-13

申请号：US17801525

申请日：2022-04-18

Applicant: Macrotest Semiconductor Inc.

Inventor： Wanchao Liu ,  Guoliang Mao

IPC: G06F11/22 ,  G06F11/263

CPC classification number: G06F11/2221 ,  G06F11/263

Abstract: The present disclosure discloses an automatic learning method and system for a digital test vector. The system includes an upper computer, a pattern generator PG, a driver DRIVER, a comparator COMPARE and a history random access memory HRAM. The method includes: writing a pattern file, the pattern file including an input pin timing and an output pin timing, wherein the input pin timing is provided by a device under test, and the output pin timing is configured to be in a learning state; running the pattern file, and recording a running state; reading recorded running state data, and acquiring an output pin state, recorded within certain time, in the running state data; and correcting the output pin timing in the running pattern file according to the acquired output pin state to obtain a corrected output timing, thus obtaining a corrected pattern file. The present disclosure greatly improves the development efficiency, reduces writing of the characteristic of an output pin of a chip, and lowers the writing difficulty.

公开(公告)号：US20240220381A1

公开(公告)日：2024-07-04

申请号：US17801527

申请日：2022-04-18

Applicant: Macrotest Semiconductor Inc.

Inventor： Guoliang Mao ,  Zhijie Bao

IPC: G06F11/273 ,  G01R31/317

CPC classification number: G06F11/2733 ,  G01R31/31727

Abstract: The present disclosure relates to a System On Chip (SOC)-oriented concurrent test system and method for multiple clock domains, and belongs to the technical field of chip detection. A board system of the present disclosure includes a board, and a clock domain controller, a slot bus controller and a test subsystem which are arranged on the board; the clock domain controller is connected to the test subsystem and the slot bus controller; the slot bus controller is connected to a backplane bus; and the test subsystem includes a test processor and a signal processing unit; the test processor includes a test pattern memory, a memory control, a timing generator, a pattern generator and a command generator. In the present disclosure, by means of a concurrent test method for multiple clock domains, the test efficiency of a single SOC is improved, and the test cost of the single chip is also reduced, thus increasing the benefit. A higher coverage rate for detecting a failure of a chip that works in a concurrent working state of multiple modules is achieved, and the yield of chips after encapsulation is increased.

公开(公告)号：US20240219451A1

公开(公告)日：2024-07-04

申请号：US17801529

申请日：2022-04-18

Applicant: Macrotest Semiconductor Inc.

Inventor： Guoliang Mao

IPC: G01R31/28

CPC classification number: G01R31/2834

Abstract: The present disclosure discloses a multi-core test processor, and an integrated circuit test system and method. The multi-core test processor includes a co-test-processor-sync-controller, a master-test-processor, two or more co-test-processors, and a test subsystem command switching device. Several co-test-processors are introduced under the master-test-processor. The master-test-processor will deliver test patterns that require concurrent testing to the co-test-processors for execution, so as to complete test items similar to the asynchronous signal match test. After the co-test-processors complete the test, the master-test-processor continues to carry out the subsequent test. The present disclosure can achieve asynchronous concurrent test on multiple sites and improve the test efficiency. Meanwhile, idling of fewer test channels can be avoided when asynchronous test channels are allocated to each site, thereby improving test channel utilization rate.