公开(公告)号：US20240220381A1

公开(公告)日：2024-07-04

申请号：US17801527

申请日：2022-04-18

Applicant: Macrotest Semiconductor Inc.

Inventor： Guoliang Mao ,  Zhijie Bao

IPC: G06F11/273 ,  G01R31/317

CPC classification number: G06F11/2733 ,  G01R31/31727

Abstract: The present disclosure relates to a System On Chip (SOC)-oriented concurrent test system and method for multiple clock domains, and belongs to the technical field of chip detection. A board system of the present disclosure includes a board, and a clock domain controller, a slot bus controller and a test subsystem which are arranged on the board; the clock domain controller is connected to the test subsystem and the slot bus controller; the slot bus controller is connected to a backplane bus; and the test subsystem includes a test processor and a signal processing unit; the test processor includes a test pattern memory, a memory control, a timing generator, a pattern generator and a command generator. In the present disclosure, by means of a concurrent test method for multiple clock domains, the test efficiency of a single SOC is improved, and the test cost of the single chip is also reduced, thus increasing the benefit. A higher coverage rate for detecting a failure of a chip that works in a concurrent working state of multiple modules is achieved, and the yield of chips after encapsulation is increased.

公开(公告)号：US12130718B2

公开(公告)日：2024-10-29

申请号：US17801527

申请日：2022-04-18

Applicant: Macrotest Semiconductor Inc.

Inventor： Guoliang Mao ,  Zhijie Bao

IPC: G06F11/273 ,  G01R31/317

CPC classification number: G06F11/2733 ,  G01R31/31727

Abstract: The present disclosure relates to a System On Chip (SOC)-oriented concurrent test system and method for multiple clock domains, and belongs to the technical field of chip detection. A board system of the present disclosure includes a board, and a clock domain controller, a slot bus controller and a test subsystem which are arranged on the board; the clock domain controller is connected to the test subsystem and the slot bus controller; the slot bus controller is connected to a backplane bus; and the test subsystem includes a test processor and a signal processing unit; the test processor includes a test pattern memory, a memory control, a timing generator, a pattern generator and a command generator. In the present disclosure, by means of a concurrent test method for multiple clock domains, the test efficiency of a single SOC is improved, and the test cost of the single chip is also reduced, thus increasing the benefit. A higher coverage rate for detecting a failure of a chip that works in a concurrent working state of multiple modules is achieved, and the yield of chips after encapsulation is increased.