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公开(公告)号：US10996283B2
公开(公告)日：2021-05-04
申请号：US15727852
申请日：2017-10-09
Applicant: INTEL CORPORATION
Inventor： Sankaran M. Menon , Vasudev Bibikar , P. Reddy Sahajananda , Sunghyun Koh , Naveendran Balasingam
IPC: G01R31/40 , G01R31/50 , G05F1/10 , G01R31/317
Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
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2.发明申请METHOD AND APPARATUS FOR ENHANCING GUARDBANDS USING "IN-SITU" SILICON MEASUREMENTS 审中-公开使用“现场”硅测量来增强保护的方法和装置公开(公告)号：US20160285434A1
公开(公告)日：2016-09-29
申请号：US14667365
申请日：2015-03-24
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Vasudev Bibikar
CPC classification number: G01R31/2637 , G06F1/3203 , H01L22/34 , H01L23/58
Abstract: A method and apparatus (e.g., semiconductor device) for setting voltages (e.g., guardbands) using “in situ,” or on-die, silicon measurements are described. In one embodiment the semiconductor device comprises: a process monitor to measure silicon parameters of the semiconductor device; and a controller coupled to the process monitor to set a voltage for use on at least a portion of the semiconductor device based on silicon process monitor measurements.
Abstract translation: 描述了使用“原地”或芯片上的硅测量来设置电压（例如，保护带）的方法和装置（例如，半导体器件）。 在一个实施例中，半导体器件包括：测量半导体器件的硅参数的工艺监控器; 以及控制器，其耦合到所述过程监视器，以基于硅过程监视器测量来设置在所述半导体器件的至少一部分上使用的电压。
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公开(公告)号：US11157374B2
公开(公告)日：2021-10-26
申请号：US16234671
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Rolf Kuehnis
Abstract: Technologies for efficiently providing reliable compute operations for mission critical applications include a reliability management system. The reliability management system includes circuitry configured to obtain conclusion data indicative of a conclusion made by each of two or fewer compute devices of a host system. The conclusion data from each compute device pertains to the same operation. Additionally, the circuitry is configured to identify whether an error has occurred in the operation of each compute device, determine, in response to a determination that an error has occurred, a severity of the error, and cause the host system to perform a responsive action as a function of the determined severity of the error.
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公开(公告)号：US09535117B2
公开(公告)日：2017-01-03
申请号：US14669693
申请日：2015-03-26
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Rolf Kuehnis
IPC: G06F11/00 , G01R31/317 , G01R31/3177
CPC classification number: G01R31/31705 , G01R31/3177 , G06F11/364
Abstract: Techniques of debugging a computing system are described herein. The techniques may include an apparatus having an all-in-one port. The all-in-one port may include a configuration channel and a sideband channel. The sideband channel is configured to default to a debug mode when the configuration channel is not communicatively coupled to an external device.
Abstract translation: 这里描述了调试计算系统的技术。 这些技术可以包括具有一体化端口的装置。 一体化端口可以包括配置信道和边带信道。 当配置通道不通信地耦合到外部设备时，边带通道被配置为默认为调试模式。
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公开(公告)号：US12183412B2
公开(公告)日：2024-12-31
申请号：US17033526
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Andrew Martyn Draper , Ting Lu , Kenneth Chen , Wei Chun Lau
Abstract: An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse.
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Patent Agency Ranking
公开(公告)号：US11709202B2
公开(公告)日：2023-07-25
申请号：US17085511
申请日：2020-10-30
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Bradley H. Smith , Jinshi Huang , Rolf H. Kuehnis
IPC: G06F11/00 , G01R31/3177 , H04W4/80 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31703 , G01R31/31705 , G01R31/31722 , H04W4/80
Abstract: Existing multi-wire debugging protocols, such as 4-wire JTAG, 2-wire cJTAG, or ARM SWD, are run through a serial wireless link by providing the debugger and the target device with hardware interfaces that include UARTs and conversion bridges. The debugger interface serializes outgoing control signals and de-serializes returning data. The target interface de-serializes incoming control signals and serializes outgoing data. The actions of the interfaces are transparent to the inner workings of the devices, allowing re-use of existing debugging software. Compression, signal combining, and other optional enhancements increase debugging speed and flexibility while wirelessly accessing target devices that may be too small, too difficult to reach, or too seal-dependent for a wired connection.
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公开(公告)号：US20220082617A1
公开(公告)日：2022-03-17
申请号：US17538482
申请日：2021-11-30
Applicant: Intel Corporation
Inventor： Rolf H. Kuehnis , Sankaran M. Menon , Patrik Eder
IPC: G01R31/3177 , G01R31/317
Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.
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8.发明申请公开(公告)号：US20190138408A1
公开(公告)日：2019-05-09
申请号：US16234671
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Rolf Kuehnis
IPC: G06F11/18
Abstract: Technologies for efficiently providing reliable compute operations for mission critical applications include a reliability management system. The reliability management system includes circuitry configured to obtain conclusion data indicative of a conclusion made by each of two or fewer compute devices of a host system. The conclusion data from each compute device pertains to the same operation. Additionally, the circuitry is configured to identify whether an error has occurred in the operation of each compute device, determine, in response to a determination that an error has occurred, a severity of the error, and cause the host system to perform a responsive action as a function of the determined severity of the error.
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公开(公告)号：US11686780B2
公开(公告)日：2023-06-27
申请号：US17232018
申请日：2021-04-15
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Vasudev Bibikar , P. Reddy Sahajananda , Sunghyun Koh , Naveendran Balasingam
IPC: G01R31/40 , G05F1/10 , G01R31/317
CPC classification number: G01R31/40 , G05F1/10 , G01R31/31725
Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
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公开(公告)号：US11193973B2
公开(公告)日：2021-12-07
申请号：US16947084
申请日：2020-07-17
Applicant: Intel Corporation
Inventor： Rolf H. Kuehnis , Sankaran M. Menon , Patrik Eder
IPC: G01R31/3177 , G01R31/317
Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.
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