公开(公告)号：US20240312975A1

公开(公告)日：2024-09-19

申请号：US18598486

申请日：2024-03-07

Applicant: Infineon Technologies Austria AG

Inventor： Horst Theuss ,  Christian Geißler ,  Walter Hartner

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/52 ,  H01L23/58 ,  H01L27/01

CPC classification number: H01L25/18 ,  H01L23/3121 ,  H01L23/58 ,  H01L23/52 ,  H01L27/01

Abstract: A transformer arrangement is disclosed. The transformer arrangement includes: an electrically insulating carrier; a first integrated circuit including a first semiconductor die embedded in or arranged on top of the electrically insulating carrier; and a transformer including a first winding and a second winding that are inductively coupled. One of the first and second windings is connected to the first integrated circuit, and each of the first and second windings is embedded in or arranged on top of the electrically insulating carrier.

公开(公告)号：US20240234345A1

公开(公告)日：2024-07-11

申请号：US18537160

申请日：2023-12-12

Applicant: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED

Inventor： Swarup BHUNIA ,  Peyman Dehghanzadeh

IPC: H01L23/58 ,  H01L23/48 ,  H01L25/18 ,  H02J7/00 ,  H03F3/45

CPC classification number: H01L23/58 ,  H01L25/18 ,  H03F3/45475 ,  H01L23/481 ,  H02J7/0063

Abstract: A three-dimensional integrated circuit is provided. In various embodiments, the three-dimensional integrated circuit includes a first electronic module disposed on a substrate of the three-dimensional integrated circuit and a first battery disposed on the first electronic module and electronically coupled to the first electronic module. The first battery may be configured to provide power to the first electronic module. The three-dimensional integrated circuit includes a second electronic module disposed on the first battery, and a second battery disposed on the second electronic module and electronically coupled to the second electronic module. The second battery may be configured to provide power to the second electronic module.

公开(公告)号：US11978694B2

公开(公告)日：2024-05-07

申请号：US17531728

申请日：2021-11-20

Applicant: JCET GROUP CO., LTD.

Inventor： Shuo Liu ,  Chen Xu ,  Yaojian Lin ,  Haitao Shi

IPC: H01L23/498 ,  H01L23/58

CPC classification number: H01L23/49816 ,  H01L23/58 ,  H01L23/49822

Abstract: The present invention provides a dual-substrate antenna package structure and a method for manufacturing the same. The package structure includes a main substrate and at least one antenna substrate. The antenna substrate is provided on a pad of the main substrate by an array of solder balls placed on the antenna substrate, at least one chip is electrically connected to the main substrate, and metal wiring provided on the main substrate electrically connects the pad to the chip. The array of solder balls includes support solder balls and conventional solder balls, and the support solder balls have a melting point high than 250° C. A spacing distance between the antenna substrate and the main substrate can be kept stable during the reflow soldering process and subsequent processes because the support solder balls having the high melting point can always maintain the stability of the structure during the reflow soldering process.

公开(公告)号：US20240096770A1

公开(公告)日：2024-03-21

申请号：US17932592

申请日：2022-09-15

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun Lee ,  HeeSoo Lee

IPC: H01L23/498 ,  H01L23/552 ,  H01L23/58 ,  H01L25/16 ,  H01Q9/04

CPC classification number: H01L23/49805 ,  H01L23/552 ,  H01L23/58 ,  H01L25/16 ,  H01Q9/0485 ,  H01R12/716

Abstract: A semiconductor device includes a first substrate. An electrical component is disposed over the first substrate. A board-to-board connector is disposed over the first substrate. An encapsulant is deposited over the first substrate and electrical component to form a subpackage. The board-to-board connector remains exposed from the encapsulant. A contact pad is formed on a side surface of the subpackage. The subpackage is mounted to an antenna through the contact pad.

公开(公告)号：US11749582B2

公开(公告)日：2023-09-05

申请号：US17874293

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Chia Lai ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hsiao-Chung Liang ,  Hao-Yi Tsai ,  Chien-Ling Hwang ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Tin-Hao Kuo ,  Chih-Hsuan Tai

IPC: H01L23/40 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/4006 ,  H01L23/58 ,  H01L24/16 ,  H01L25/18 ,  H01L2023/405 ,  H01L2023/4068 ,  H01L2023/4087 ,  H01L2224/023 ,  H01L2224/16145

Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

公开(公告)号：US20230261572A1

公开(公告)日：2023-08-17

申请号：US18305442

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Alan Roth ,  Haohua Zhou ,  Eric Soenen ,  Ying-Chih Hsu ,  Paul Ranucci ,  Mei Hsu Wong ,  Tze-Chiang Huang

IPC: H02M3/156 ,  H01L23/498 ,  H01L23/58 ,  H01L23/495

CPC classification number: H02M3/156 ,  H01L23/49811 ,  H01L23/58 ,  H01L23/49838 ,  H01L23/49589

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

公开(公告)号：US20230197747A1

公开(公告)日：2023-06-22

申请号：US18167972

申请日：2023-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOONBAE KIM

IPC: H01L27/146 ,  H01L23/58 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L27/14621 ,  H01L27/14627 ,  H01L27/14603 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14634 ,  H01L27/14625 ,  H01L23/58 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/06 ,  H01L27/1462 ,  H01L23/02

Abstract: A semiconductor package may include an image sensor chip, a transparent substrate spaced apart from the image sensor chip, a joining structure in contact with a top surface of the image sensor chip and a bottom surface of the transparent substrate, on an edge region of the top surface of the image sensor chip, and a circuit substrate electrically connected to the image sensor chip. The image sensor chip may include a penetration electrode which penetrates at least a portion of an internal portion of the image sensor chip, and a terminal pad, which is on the edge region of the top surface of the image sensor chip and is electrically connected to the penetration electrode. The joining structure may include a spacer and an adhesive layer. The joining structure may overlap the terminal pad. The spacer is between the transparent substrate and the terminal pad.

公开(公告)号：US11671010B2

公开(公告)日：2023-06-06

申请号：US16991335

申请日：2020-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alan Roth ,  Haohua Zhou ,  Eric Soenen ,  Ying-Chih Hsu ,  Paul Ranucci ,  Mei Hsu Wong ,  Tze-Chiang Huang

IPC: H02M3/156 ,  H01L23/498 ,  H01L23/58 ,  H01L23/495

CPC classification number: H02M3/156 ,  H01L23/49589 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/58

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

公开(公告)号：US11670603B2

公开(公告)日：2023-06-06

申请号：US17366842

申请日：2021-07-02

Applicant: X-Celeprint Limited

Inventor： António José Marques Trindade ,  Ronald S. Cok

IPC: H01L23/58 ,  H01L23/544

CPC classification number: H01L23/58 ,  H01L23/544 ,  H01L2223/54426

Abstract: A micro-component comprises a component substrate having a first side and an opposing second side. Fenders project from the first and second sides of the component substrate and include first-side fenders extending from the first side and a second-side fender extending from the second side of the component substrate. At least two of the first-side fenders have a non-conductive surface and are disposed closer to a corner of the component substrate than to a center of the component substrate.

公开(公告)号：US20190244988A1

公开(公告)日：2019-08-08

申请号：US16386665

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Han Tsai ,  Chun-Hao Chou ,  Kuo-Cheng Lee ,  Yung-Lung Hsu ,  Yun-Wei Cheng

IPC: H01L27/146 ,  H01L23/58 ,  H01L21/761

CPC classification number: H01L27/1463 ,  H01L21/761 ,  H01L23/58 ,  H01L27/14607 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14687 ,  H01L27/14689

Abstract: Some embodiments relate to a device array including a plurality of devices arranged in a semiconductor substrate. A protection ring circumscribes an outer perimeter of the device array. The protection ring includes a first ring neighboring the device array, a second ring circumscribing the first ring and meeting the first ring at a first p-n junction, and a third ring circumscribing the second ring and meeting the second ring at a second p-n junction. The first ring has a first width, the second ring has a second width, and the third ring has a third width. At least two of the first width, the second width, and the third width are different from one another.