公开(公告)号：US20230378040A1

公开(公告)日：2023-11-23

申请号：US18359909

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sung-Yueh Wu ,  Chien-Ling Hwang ,  Jen-Chun Liao ,  Ching-Hua Hsieh ,  Pei-Hsuan Lee ,  Chia-Hung Liu

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/48

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L23/3128 ,  H01L23/49833 ,  H01L21/486 ,  H01L21/4857 ,  H01L24/73

摘要： A package structure includes a carrier substrate, a die, and an encapsulant. The carrier substrate includes through carrier vias (TCV). The die is disposed over the carrier substrate. The die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. The conductive posts face away from the carrier substrate. The encapsulant laterally encapsulates the die.

公开(公告)号：US20220319903A1

公开(公告)日：2022-10-06

申请号：US17367631

申请日：2021-07-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jen-Chun Liao ,  Sung-Yueh Wu ,  Chien-Ling Hwang ,  Ching-Hua Hsieh

IPC分类号： H01L21/683 ,  H01L21/687

摘要： An apparatus and a method for handling a semiconductor substrate are provided. The apparatus includes a chuck table and a first flexible member. The chuck table includes a carrying surface, a first recess provided within the carrying surface, and a vacuum channel disposed below the carrying surface, and the chuck table is configured to hold the semiconductor substrate. The first flexible member is disposed within the first recess and includes a top surface protruded from the first recess, and the first flexible member is compressed as the semiconductor substrate presses against the first flexible member.

公开(公告)号：US20240356199A1

公开(公告)日：2024-10-24

申请号：US18762578

申请日：2024-07-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pei-Hsuan Lee ,  Ching-Hua Hsieh ,  Chien-Ling Hwang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC分类号： H01Q1/22 ,  H01L21/48 ,  H01L23/00 ,  H01L23/66 ,  H01Q1/40

CPC分类号： H01Q1/2283 ,  H01L21/4846 ,  H01L23/66 ,  H01L24/13 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01Q1/40 ,  H01L2223/6677 ,  H01L2224/13024 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267

摘要： A method of manufacturing an electronic device includes: providing a composite structure, wherein the composite structure comprises a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer; thinning the two conductive layers to form two thinned conductive layers; forming an antenna pattern using one of the two thinned conductive layers; forming an antenna package to encapsulate the antenna pattern therein; forming a circuit pattern by patterning the other one of the two thinned conductive layers; and forming a chip package to encapsulate the circuit pattern therein, wherein the chip package is electrically coupled to the antenna package.

公开(公告)号：US20240332132A1

公开(公告)日：2024-10-03

申请号：US18740523

申请日：2024-06-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jen-Chun Liao ,  Sung-Yueh Wu ,  Chien-Ling Hwang ,  Ching-Hua Hsieh

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/481 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386

摘要： A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.

公开(公告)号：US11749582B2

公开(公告)日：2023-09-05

申请号：US17874293

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chia Lai ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hsiao-Chung Liang ,  Hao-Yi Tsai ,  Chien-Ling Hwang ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Tin-Hao Kuo ,  Chih-Hsuan Tai

IPC分类号： H01L23/40 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

CPC分类号： H01L23/4006 ,  H01L23/58 ,  H01L24/16 ,  H01L25/18 ,  H01L2023/405 ,  H01L2023/4068 ,  H01L2023/4087 ,  H01L2224/023 ,  H01L2224/16145

摘要： A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

公开(公告)号：US20220359343A1

公开(公告)日：2022-11-10

申请号：US17874293

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chia Lai ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hsiao-Chung Liang ,  Hao-Yi Tsai ,  Chien-Ling Hwang ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Tin-Hao Kuo ,  Chih-Hsuan Tai

IPC分类号： H01L23/40 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

摘要： A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

公开(公告)号：US20220278023A1

公开(公告)日：2022-09-01

申请号：US17185966

申请日：2021-02-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jen-Chun Liao ,  Sung-Yueh Wu ,  Chien-Ling Hwang ,  Ching-Hua Hsieh

IPC分类号： H01L23/48 ,  H01L23/15 ,  H01L21/768 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

摘要： A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.

公开(公告)号：US20210351491A1

公开(公告)日：2021-11-11

申请号：US17383403

申请日：2021-07-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pei-Hsuan Lee ,  Ching-Hua Hsieh ,  Chien-Ling Hwang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC分类号： H01Q1/22 ,  H01L23/00 ,  H01L21/48 ,  H01Q1/40 ,  H01L23/66

摘要： A method of manufacturing an electronic device includes providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer, and removing at least a portion of each of the two conductive layers to respectively form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.

公开(公告)号：US20240262096A1

公开(公告)日：2024-08-08

申请号：US18165933

申请日：2023-02-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Ting Chiu ,  Ying-Jui Huang ,  Chien-Ling Hwang ,  Ching-Hua Hsieh

IPC分类号： B32B37/18

CPC分类号： B32B37/18 ,  B32B2307/204 ,  B32B2307/538 ,  B32B2307/732 ,  B32B2309/02 ,  B32B2309/68 ,  B32B2319/00 ,  B32B2457/14 ,  H01L21/4853 ,  H01L21/568 ,  H01L24/19 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/19 ,  H01L2224/8385

摘要： A method for laminating a film to a wafer and apparatus for performing the lamination process are disclosed. The method includes providing the wafer and the film in a process chamber where the wafer and the film are separated from each other, achieving a vacuum state and a process temperature in the process chamber, and laminating the film to contact a surface of the wafer.

公开(公告)号：US12040247B2

公开(公告)日：2024-07-16

申请号：US17320198

申请日：2021-05-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pei-Hsuan Lee ,  Ching-Hua Hsieh ,  Chien-Ling Hwang

IPC分类号： H01L23/36 ,  H01L21/50 ,  H01L23/40

CPC分类号： H01L23/36 ,  H01L21/50 ,  H01L23/40

摘要： A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.