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    SCHEDULER
    3.
    发明申请
    SCHEDULER 审中-公开

    公开(公告)号：US20170228301A1

    公开(公告)日：2017-08-10

    申请号：US15495899

    申请日：2017-04-24

    Applicant: Advantest Corporation

    Inventor： Peter Schinzel

    IPC: G06F11/273 ,  G01R31/317 ,  G01R31/319

    CPC classification number: G06F11/2733 ,  G01R31/31724 ,  G01R31/31903

    Abstract: Embodiments provide a scheduler for scheduling test times of a plurality of tester software environments for an automatic test equipment. The scheduler is configured to automatically assign test times to the plurality of tester software environments, to acquire test instructions from a tester software environment of the plurality of tester software environments to which a current test time is assigned, to control the automatic test equipment to perform a test according to the test instructions in order to obtain test results, and to provide the test results to the tester software environment of the plurality of tester software environments to which the current test time is assigned.

    Method and apparatus for device testing using multiple processing paths
    6.
    发明授权
    Method and apparatus for device testing using multiple processing paths 有权
    使用多个处理路径进行设备测试的方法和装置

    公开(公告)号：US09134377B2

    公开(公告)日：2015-09-15

    申请号：US13826038

    申请日：2013-03-14

    Applicant: Corbin Champion ,  John R. Pane ,  Mark B. Donahue

    Inventor： Corbin Champion ,  John R. Pane ,  Mark B. Donahue

    IPC: G01R31/3177 ,  G01R31/3183 ,  G06F9/32 ,  G01R31/319

    CPC classification number: G01R31/318307 ,  G01R31/3177 ,  G01R31/31903 ,  G01R31/31917 ,  G01R31/31919 ,  G06F9/322

    Abstract: According to some aspects, a method of operating an automatic test system comprising a plurality of paths and programmed with a test pattern is provided. One such method comprises executing vectors in the test pattern with circuitry comprising a plurality of paths, the executing comprising upon processing, in a first of the plurality of paths, the operation portion of a vector specifying an operation capable of generating a branch in the flow of execution of the vectors in the test pattern to a non-sequential location in the test pattern, initiating processing of the test pattern in a second of the plurality of paths from the non-sequential location. Some aspects include a system for executing instructions comprising a plurality of paths comprising control circuitry to initiate processing of operation portions from sequential locations of a memory within an available path of the plurality of paths.

    Abstract translation: 根据一些方面，提供一种操作包括多个路径并用测试图案编程的自动测试系统的方法。 一种这样的方法包括在包括多个路径的电路中执行测试模式中的向量，所述执行包括在所述多个路径中的第一个路径中处理指定能够在所述流中生成分支的操作​​的向量的操作部分 将所述测试模式中的所述向量执行到所述测试模式中的非顺序位置，从所述非顺序位置开始处理所述多个路径中的第二路径中的所述测试模式。 一些方面包括用于执行指令的系统，其包括多个路径，其包括控制电路，以从多个路径的可用路径内的存储器的顺序位置开始处理操作部分。

    Multi-tier field-programmable gate array hardware requirements assessment and verification for airborne electronic systems
    7.
    发明授权
    Multi-tier field-programmable gate array hardware requirements assessment and verification for airborne electronic systems 有权
    机载电子系统的多层现场可编程门阵列硬件要求评估和验证

    公开(公告)号：US08856708B1

    公开(公告)日：2014-10-07

    申请号：US13940863

    申请日：2013-07-12

    Applicant: Hamilton Sundstrand Corporation

    Inventor： Kirk A. Lillestolen

    IPC: G06F17/50

    CPC classification number: G01R31/318519 ,  G01R31/008 ,  G01R31/318357 ,  G01R31/31903 ,  G06F17/5054

    Abstract: A method of verifying a field programmable gate array for use in an integrated system includes selecting, from a set of requirements of the field programmable gate array, a first subset of the requirements that are not influenced by dynamics of the integrated system; selecting, from the set of requirements of the field programmable gate array, a second subset of the requirements that are influenced by the dynamics of the integrated system; executing a hardware test on the field programmable gate array using a chip tester that verifies the first subset of the requirements; and executing a hardware test on the field programmable gate array to verify the second subset of the requirements while the field programmable gate array is installed within the integrated system.

    Abstract translation: 验证在集成系统中使用的现场可编程门阵列的方法包括从现场可编程门阵列的一组要求中选择不受集成系统的动态影响的要求的第一子集; 从现场可编程门阵列的一组要求中选择受集成系统的动力学影响的要求的第二子集; 使用验证要求的第一个子集的芯片测试器对现场可编程门阵列执行硬件测试; 并且在现场可编程门阵列上执行硬件测试以验证所述要求的第二子集，同时将现场可编程门阵列安装在集成系统内。

    METHOD AND APPARATUS FOR DEVICE TESTING USING MULTIPLE PROCESSING PATHS
    8.
    发明申请
    METHOD AND APPARATUS FOR DEVICE TESTING USING MULTIPLE PROCESSING PATHS 有权
    使用多种处理方式进行设备测试的方法和装置

    公开(公告)号：US20140281776A1

    公开(公告)日：2014-09-18

    申请号：US13826038

    申请日：2013-03-14

    Applicant: Corbin L. Champion ,  John R. Pane ,  Mark B. Donahue

    Inventor： Corbin L. Champion ,  John R. Pane ,  Mark B. Donahue

    IPC: G01R31/3177

    CPC classification number: G01R31/318307 ,  G01R31/3177 ,  G01R31/31903 ,  G01R31/31917 ,  G01R31/31919 ,  G06F9/322

    Abstract: According to some aspects, a method of operating an automatic test system comprising a plurality of paths and programmed with a test pattern is provided. One such method comprises executing vectors in the test pattern with circuitry comprising a plurality of paths, the executing comprising upon processing, in a first of the plurality of paths, the operation portion of a vector specifying an operation capable of generating a branch in the flow of execution of the vectors in the test pattern to a non-sequential location in the test pattern, initiating processing of the test pattern in a second of the plurality of paths from the non-sequential location. Some aspects include a system for executing instructions comprising a plurality of paths comprising control circuitry to initiate processing of operation portions from sequential locations of a memory within an available path of the plurality of paths.

    Abstract translation: 根据一些方面，提供一种操作包括多个路径并用测试图案编程的自动测试系统的方法。 一种这样的方法包括在包括多个路径的电路中执行测试模式中的向量，执行包括在多个路径中的第一个路径中处理指定可以在该流中生成分支的操作​​的向量的向量的操作部分 将所述测试模式中的所述向量执行到所述测试模式中的非顺序位置，从所述非顺序位置开始处理所述多个路径中的第二路径中的所述测试模式。 一些方面包括用于执行指令的系统，其包括多个路径，其包括控制电路，以从多个路径的可用路径内的存储器的顺序位置开始处理操作部分。

    TEST ARCHITECTURE HAVING MULTIPLE FPGA BASED HARDWARE ACCELERATOR BLOCKS FOR TESTING MULTIPLE DUTS INDEPENDENTLY
    9.
    发明申请
    TEST ARCHITECTURE HAVING MULTIPLE FPGA BASED HARDWARE ACCELERATOR BLOCKS FOR TESTING MULTIPLE DUTS INDEPENDENTLY 审中-公开
    具有多个基于FPGA的硬件加速器块的测试架构独立测试多个单独的

    公开(公告)号：US20140236525A1

    公开(公告)日：2014-08-21

    申请号：US13773569

    申请日：2013-02-21

    Applicant: ADVANTEST CORPORATION

    Inventor： Gerald CHAN ,  Eric KUSHNICK ,  Mei-Mei SU ,  Andrew NIEMIC

    IPC: G01R31/26

    CPC classification number: G01R31/31907 ,  G01R31/31724 ,  G01R31/31903 ,  G01R31/31919 ,  G06F11/263 ,  G11C29/56

    Abstract: Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.

    Abstract translation: 介绍了能够进行半导体器件测试的自动测试设备（ATE）。 ATE包括计算机系统，其包括通信地耦合到测试器处理器的系统控制器。 系统控制器可操作以将指令发送到处理器，并且处理器可操作以从用于协调测试的多个被测设备（DUT）的测试的指令生成命令和数据。 ATE还包括通过总线通信地耦合到处理器的多个FPGA组件。 每个FPGA组件包括至少一个硬件加速器电路，其可操作以从处理器透明地内部地生成命令和数据，以测试DUT中的一个。 另外，测试器处理器被配置为在几种功能模式之一中操作，其中功能模式被配置为分配用于在处理器和FPGA组件之间产生命令和数据的功能。

    INTEGRATED DEFECT DETECTION AND LOCATION SYSTEMS AND METHODS IN SEMICONDUCTOR CHIP DEVICES
    10.
    发明申请
    INTEGRATED DEFECT DETECTION AND LOCATION SYSTEMS AND METHODS IN SEMICONDUCTOR CHIP DEVICES 审中-公开
    集成缺陷检测和位置系统和半导体芯片设备的方法

    公开(公告)号：US20140013171A1

    公开(公告)日：2014-01-09

    申请号：US13541063

    申请日：2012-07-03

    Applicant: Cheow Guan Lim ,  Giovanni Ferrara

    Inventor： Cheow Guan Lim ,  Giovanni Ferrara

    IPC: G01R31/3177

    CPC classification number: G01R31/3187 ,  G01R31/318533 ,  G01R31/318558 ,  G01R31/318561 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/319 ,  G01R31/31903 ,  G01R31/31915

    Abstract: Embodiments relate to systems and methods for defect detection and localization in semiconductor chips. In an embodiment, a plurality of registers is arranged in a semiconductor chip. The particular number of registers can vary according to a desired level of localization, and the plurality of registers are geometrically distributed such that defect detection and localization over the entire chip area or a desired chip area, such as a central active region, is achieved in embodiments. In operation, a defect detection and localization routine can be run in parallel with other normal chip functions during a power-up or other phase. In embodiments, the registers can be multi-functional in that they can be used for other operational functions of the chip when not used for defect detection and localization, and vice-versa. Embodiments thereby provide fast, localized defect detection.

    Abstract translation: 实施例涉及用于半导体芯片中的缺陷检测和定位的系​​统和方法。 在一个实施例中，多个寄存器布置在半导体芯片中。 特定数量的寄存器可以根据所需的定位水平而变化，并且多个寄存器是几何分布的，使得在整个芯片区域或期望的芯片区域（例如中心有源区域）上的缺陷检测和定位在 实施例。 在运行中，缺陷检测和定位程序可以在上电或其他阶段与其他正常芯片功能并行运行。 在实施例中，寄存器可以是多功能的，因为当不用于缺陷检测和定位时，它们可以用于芯片的其他操作功能，反之亦然。 因此，实施例提供了快速的局部缺陷检测。

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