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    LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME
    2.
    发明申请
    LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME 有权

    公开(公告)号：US20230123956A1

    公开(公告)日：2023-04-20

    申请号：US18068666

    申请日：2022-12-20

    Applicant: NVIDIA Corporation

    Inventor： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

    IPC: G06F11/267 ,  G06F11/22 ,  G06F1/3296 ,  G06F11/273 ,  G06F11/27

    Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

    PERFORMING TESTING UTILIZING STAGGERED CLOCKS
    3.
    发明申请
    PERFORMING TESTING UTILIZING STAGGERED CLOCKS 有权

    公开(公告)号：US20230089800A1

    公开(公告)日：2023-03-23

    申请号：US17478736

    申请日：2021-09-17

    Applicant: NVIDIA Corporation

    Inventor： Sailendra Chadalavada ,  Venkat Abilash Reddy Nerallapally ,  Jaison Daniel Kurien ,  Bonita Bhaskaran ,  Milind Sonawane ,  Shantanu Sarangi ,  Purnabha Majumder

    IPC: G01R31/3177

    Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

    Leveraging low power states for fault testing of processing cores at runtime
    4.
    发明授权
    Leveraging low power states for fault testing of processing cores at runtime 有权

    公开(公告)号：US11573872B2

    公开(公告)日：2023-02-07

    申请号：US17556473

    申请日：2021-12-20

    Applicant: NVIDIA Corporation

    Inventor： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

    IPC: G06F11/267 ,  G06F11/22 ,  G06F11/273 ,  G06F11/27 ,  G06F1/3296

    Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

    CONTROLLING TEST NETWORKS OF CHIPS USING INTEGRATED PROCESSORS
    5.
    发明申请
    CONTROLLING TEST NETWORKS OF CHIPS USING INTEGRATED PROCESSORS 有权

    公开(公告)号：US20220138387A1

    公开(公告)日：2022-05-05

    申请号：US17089864

    申请日：2020-11-05

    Applicant: Nvidia Corporation

    Inventor： Kaushik Narayanun ,  Mahmut Yilmaz ,  Shantanu Sarangi ,  Jae Wu

    IPC: G06F30/33 ,  G06F30/323 ,  G06F30/392 ,  G06T1/20

    Abstract: The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

    GRANULAR DYNAMIC TEST SYSTEMS AND METHODS
    7.
    发明申请
    GRANULAR DYNAMIC TEST SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20170115353A1

    公开(公告)日：2017-04-27

    申请号：US15336716

    申请日：2016-10-27

    Applicant: NVIDIA CORPORATION

    Inventor： Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Bala Tarun Nelapatla ,  Shantanu Sarangi ,  Rajendra Kumar reddy.S

    IPC: G01R31/317 ,  G01R31/3177

    Abstract: In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.

    In system test of chips in functional systems
    10.
    发明授权
    In system test of chips in functional systems 有权

    公开(公告)号：US11408934B2

    公开(公告)日：2022-08-09

    申请号：US16230929

    申请日：2018-12-21

    Applicant: Nvidia Corporation

    Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

    IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/14 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G01R31/3181 ,  G01R31/3185 ,  G06F11/273

    Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

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