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公开(公告)号：US09250645B2
公开(公告)日：2016-02-02
申请号：US14198790
申请日：2014-03-06
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.
摘要翻译： 公开了一种电子系统，其可以包括相位流水线，数据流水线，输入相位选择器和输出相位选择器。 相位流水线可以具有由时钟信号计时的锁存器，并被设计成将相位信号从相位输入传播到相位输出。 数据流水线可以具有由相位流水线时钟信号定时的锁存器，并被设计为将数据从数据输入传播到数据输出。 输入相位选择器可以被设计为响应于相位输入处的数据，向数据输入端提供来自数据输入端的数据的反相或非反相副本到数据流水线数据输入端。 输出相位选择器可以被设计为响应于相位流水线输出值，将来自数据流水线输出的数据的反相或非反相副本提供给输出相位选择器数据输出。
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公开(公告)号：US20150253808A1
公开(公告)日：2015-09-10
申请号：US14280782
申请日：2014-05-19
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.
摘要翻译： 公开了一种电子系统，其可以包括相位流水线，数据流水线，输入相位选择器和输出相位选择器。 相位流水线可以具有由时钟信号计时的锁存器，并被设计成将相位信号从相位输入传播到相位输出。 数据流水线可以具有由相位流水线时钟信号定时的锁存器，并被设计为将数据从数据输入传播到数据输出。 输入相位选择器可以被设计为响应于相位输入处的数据，向数据输入端提供来自数据输入端的数据的反相或非反相副本到数据流水线数据输入端。 输出相位选择器可以被设计为响应于相位流水线输出值，将来自数据流水线输出的数据的反相或非反相副本提供给输出相位选择器数据输出。
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公开(公告)号：US09383767B2
公开(公告)日：2016-07-05
申请号：US14280782
申请日：2014-05-19
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.
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公开(公告)号：US20150253807A1
公开(公告)日：2015-09-10
申请号：US14198790
申请日：2014-03-06
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.
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公开(公告)号：US08943458B1
公开(公告)日：2015-01-27
申请号：US14027594
申请日：2013-09-16
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
IPC分类号： G06F17/50
CPC分类号： G06F11/2236 , G06F11/263 , G11C29/06
摘要： Various embodiments include approaches for determining burn-in workload conditions for an integrated circuit (IC) design. Some embodiments include burn-in testing the IC design using the workload conditions. In some embodiments, a computer implemented method includes obtaining survey data about at least one application workload for an integrated circuit (IC) corresponding to an IC design; generating latch state and clocking statistics about the IC design for the at least one application workload based upon the survey data; and determining a set of burn-in workload conditions for the IC design based upon the latch state and clocking statistics about the IC design.
摘要翻译： 各种实施例包括用于确定集成电路（IC）设计的老化工作负载条件的方法。 一些实施例包括使用工作负载条件对IC设计进行老化测试。 在一些实施例中，计算机实现的方法包括获得关于与IC设计相对应的集成电路（IC）的至少一个应用工作负载的调查数据; 基于所述调查数据产生关于所述至少一个应用工作负载的IC设计的锁存状态和时钟统计; 以及基于关于IC设计的锁存状态和时钟统计来确定用于IC设计的一组老化工作负载条件。
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