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公开(公告)号：US10572617B2
公开(公告)日：2020-02-25
申请号：US15794554
申请日：2017-10-26
IPC分类号： G06F17/50 , G01R31/317
摘要： A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.
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公开(公告)号：US09928127B2
公开(公告)日：2018-03-27
申请号：US15010088
申请日：2016-01-29
IPC分类号： G06F11/00 , G06F11/07 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0842 , G06F12/0875 , G06F12/0891 , G06F12/0897 , G06F11/22 , G06F11/14 , G06F11/26
CPC分类号： G06F11/0724 , G06F11/141 , G06F11/1474 , G06F11/2242 , G06F11/261 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0842 , G06F12/0875 , G06F12/0891 , G06F12/0897 , G06F2212/1032 , G06F2212/452 , G06F2212/6042 , G06F2212/621
摘要： Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.
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公开(公告)号：US20170344679A1
公开(公告)日：2017-11-30
申请号：US15293777
申请日：2016-10-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/14
摘要： A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.
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公开(公告)号：US20170220439A1
公开(公告)日：2017-08-03
申请号：US15197534
申请日：2016-06-29
IPC分类号： G06F11/263 , G06F11/22 , G06F12/08
CPC分类号： G06F11/0724 , G06F11/141 , G06F11/1474 , G06F11/2242 , G06F11/261 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0842 , G06F12/0875 , G06F12/0891 , G06F12/0897 , G06F2212/1032 , G06F2212/452 , G06F2212/6042 , G06F2212/621
摘要： Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.
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公开(公告)号：US10678974B2
公开(公告)日：2020-06-09
申请号：US15794531
申请日：2017-10-26
IPC分类号： G06F30/30 , G01R31/317 , G06F30/33 , G06F30/333
摘要： A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.
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公开(公告)号：US20170220437A1
公开(公告)日：2017-08-03
申请号：US15010088
申请日：2016-01-29
IPC分类号： G06F11/263 , G06F11/22 , G06F12/08
CPC分类号： G06F11/0724 , G06F11/141 , G06F11/1474 , G06F11/2242 , G06F11/261 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0842 , G06F12/0875 , G06F12/0891 , G06F12/0897 , G06F2212/1032 , G06F2212/452 , G06F2212/6042 , G06F2212/621
摘要： Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.
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公开(公告)号：US11321146B2
公开(公告)日：2022-05-03
申请号：US16407819
申请日：2019-05-09
发明人： Ralf Winkelmann , Michael Fee , Matthias Klein , Carsten Otte , Edward W. Chencinski , Hanno Eichelberger
IPC分类号： G06F9/46 , G06F9/52 , G06F12/084 , G06F12/0842 , G06F9/54
摘要： The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.
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公开(公告)号：US09934343B2
公开(公告)日：2018-04-03
申请号：US15166384
申请日：2016-05-27
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/14
摘要： A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.
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公开(公告)号：US09928321B2
公开(公告)日：2018-03-27
申请号：US15293777
申请日：2016-10-14
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/14
摘要： A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.
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公开(公告)号：US20180046743A1
公开(公告)日：2018-02-15
申请号：US15794554
申请日：2017-10-26
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/14
摘要： A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.
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