公开(公告)号：US11586265B2

公开(公告)日：2023-02-21

申请号：US17349476

申请日：2021-06-16

Applicant: International Business Machines Corporation

Inventor： Pradeep Bhadravati Parashurama ,  Alper Buyuktosunoglu ,  Ramon Bertran Monfort ,  Tobias Webel ,  Martin Recktenwald ,  Preetham M. Lobo ,  Srinivas Bangalore Purushotham

IPC: G06F1/30

Abstract: Embodiments relate to a system, program product, and method for proactively initiating throttle action on one or more cores in a multicore processing device to mitigate voltage droop therein. The method includes determining, in real-time, an indication of stall events within the core and determining one or more resolutions of the stall events. The method also includes determining, in real-time, a timing margin value for the core and predicting inducement of a voltage droop on the core. The method further includes integrating the resolutions of the stall events and the timing margin value for the core, determining, subject to the predicting, a throttle action for the core, and executing the throttle action on the core.

公开(公告)号：US11281469B2

公开(公告)日：2022-03-22

申请号：US17122084

申请日：2020-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Martin Recktenwald ,  Donald W. Schmidt ,  Timothy Slegel ,  Aditya N. Puranik ,  Mark S. Farrell ,  Christian Jacobi ,  Jonathan D. Bradbury ,  Christian Zoellin

IPC: G06F9/30 ,  G06F9/38

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

公开(公告)号：US20210026783A1

公开(公告)日：2021-01-28

申请号：US17069290

申请日：2020-10-13

Applicant: International Business Machines Corporation

Inventor： Markus Helms ,  Christian Jacobi ,  Ulrich Mayer ,  Martin Recktenwald ,  Johannes C. Reichart ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/1045 ,  G06F12/0864 ,  G06F12/0842 ,  G06F12/0808 ,  G06F12/0817 ,  G06F12/1009

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

公开(公告)号：US10831478B2

公开(公告)日：2020-11-10

申请号：US16181923

申请日：2018-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Martin Recktenwald ,  Donald W. Schmidt ,  Timothy Slegel ,  Aditya N. Puranik ,  Mark S. Farrell ,  Christian Jacobi ,  Jonathan D. Bradbury ,  Christian Zoellin

IPC: G06F9/30

Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

公开(公告)号：US20200348940A1

公开(公告)日：2020-11-05

申请号：US16933037

申请日：2020-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Martin Recktenwald ,  Donald W. Schmidt ,  Timothy Slegel ,  Aditya N. Puranik ,  Mark S. Farrell ,  Christian Jacobi ,  Jonathan D. Bradbury ,  Christian Zoellin

IPC: G06F9/38 ,  G06F9/30

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

公开(公告)号：US10713168B2

公开(公告)日：2020-07-14

申请号：US15844084

申请日：2017-12-15

Applicant: International Business Machines Corporation

Inventor： Christian Jacobi ,  Ulrich Mayer ,  Martin Recktenwald ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/0831 ,  G06F12/1045 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/1027

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

公开(公告)号：US10671532B2

公开(公告)日：2020-06-02

申请号：US15833444

申请日：2017-12-06

Applicant: International Business Machines Corporation

Inventor： Christian Zoellin ,  Christian Jacobi ,  Chung-Lung K. Shum ,  Martin Recktenwald ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/0817 ,  G06F12/0831 ,  G06F12/0842

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

公开(公告)号：US20200142705A1

公开(公告)日：2020-05-07

申请号：US16181751

申请日：2018-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Martin Recktenwald ,  Donald W. Schmidt ,  Timothy Slegel ,  Aditya N. Puranik ,  Mark S. Farrell ,  Christian Jacobi ,  Jonathan D. Bradbury ,  Christian Zoellin

IPC: G06F9/38 ,  G06F9/30

Abstract: Migration of partially completed instructions. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. The instruction is re-executed on a selected processor to resume forward processing of the instruction. The re-executing includes determining whether model-dependent metadata is to be used by the selected processor in re-executing the instruction. Based on determining the model-dependent metadata is to be used, the model-dependent metadata is used in re-executing the instruction. Based on determining the model-dependent metadata is not to be used, proceeding with re-executing the instruction without using the model-dependent metadata.

公开(公告)号：US10579332B1

公开(公告)日：2020-03-03

申请号：US16118560

申请日：2018-08-31

Applicant: International Business Machines Corporation

Inventor： Christian Jacobi ,  Aditya Puranik ,  Martin Recktenwald ,  Christian Zoellin

IPC: G06F7/16 ,  G06F7/02 ,  G06F7/24 ,  G06F7/36 ,  G06F7/08 ,  G06F9/50

Abstract: A computer processor includes a memory unit that stores key values to be loaded into a partial tournament sort, and a processor cache that obtains tree data from the memory unit indicating the key values. A hardware merge sort accelerator generates a tournament tree based on the key values, and performs a partial tournament sort to store a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache.

公开(公告)号：US10528482B2

公开(公告)日：2020-01-07

申请号：US15996646

申请日：2018-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Deanna P. D. Berger ,  Christian Jacobi ,  Martin Recktenwald ,  Yossi Shapira ,  Aaron Tsai

IPC: G06F12/12 ,  G06F12/123 ,  G06F12/0817 ,  G06F12/0811 ,  G06F12/02 ,  G06F12/084

Abstract: A method, a computer system, and a computer program product to perform a directory lookup in a first level cache for requested cache line data. A first processor core can detect that the requested cache line data is not found in a plurality of sets of data in the first level cache and detect that existing cache line data stored in a least recently used data set stored in the first level cache is in an exclusive state, wherein the existing cache line data stored in the least recently used data set is to be overwritten by the requested cache line data retrieved from a second level cache. Furthermore, the first processor core can send a request for the requested cache line data and a physical address of the least recently used data set to the second level cache and execute additional instructions based on the first level cache and data retrieved from the second level cache.