公开(公告)号：US10956337B2

公开(公告)日：2021-03-23

申请号：US16561352

申请日：2019-09-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Christian Jacobi ,  Daniel V. Rosa ,  Anthony Saporito ,  Donald W. Schmidt ,  Chung-Lung K. Shum

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/38 ,  G06F13/42

Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

公开(公告)号：US20210011719A1

公开(公告)日：2021-01-14

申请号：US17037962

申请日：2020-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Martin Recktenwald ,  Donald W. Schmidt ,  Timothy Slegel ,  Aditya N. Puranik ,  Mark S. Farrell ,  Christian Jacobi ,  Jonathan D. Bradbury ,  Christian Zoellin

IPC: G06F9/30

Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

公开(公告)号：US10831502B2

公开(公告)日：2020-11-10

申请号：US16181751

申请日：2018-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Martin Recktenwald ,  Donald W. Schmidt ,  Timothy Slegel ,  Aditya N. Puranik ,  Mark S. Farrell ,  Christian Jacobi ,  Jonathan D. Bradbury ,  Christian Zoellin

IPC: G06F9/38 ,  G06F9/30

Abstract: Migration of partially completed instructions. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. The instruction is re-executed on a selected processor to resume forward processing of the instruction. The re-executing includes determining whether model-dependent metadata is to be used by the selected processor in re-executing the instruction. Based on determining the model-dependent metadata is to be used, the model-dependent metadata is used in re-executing the instruction. Based on determining the model-dependent metadata is not to be used, proceeding with re-executing the instruction without using the model-dependent metadata.

公开(公告)号：US10554525B2

公开(公告)日：2020-02-04

申请号：US15823706

申请日：2017-11-28

Applicant: International Business Machines Corporation

Inventor： Robert Abrams ,  Donald W. Schmidt ,  Andrew M. Sica ,  Horst Sinram

IPC: G06F17/30 ,  H04L12/26 ,  H04L29/06 ,  H04L12/911

Abstract: Systems and methods for tracking computing resources are provided. Aspects include receiving, by a workload manager, a workload, wherein the workload is executable on a customer machine, and wherein the customer machine comprises a plurality of computing resources. The workload is analyzed to determine a workload profile. A token associated with the workload is received and associated with the workload profile. The token is authenticated and the workload is executed based at least in part on authentication of the token.

公开(公告)号：US10521351B2

公开(公告)日：2019-12-31

申请号：US15404254

申请日：2017-01-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Christian Jacobi ,  Daniel V. Rosa ,  Anthony Saporito ,  Donald W. Schmidt ,  Chung-Lung K. Shum

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0842 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F12/0862 ,  G06F9/38 ,  G06F13/42

Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

公开(公告)号：US20190324682A1

公开(公告)日：2019-10-24

申请号：US16502323

申请日：2019-07-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jane H. Bartik ,  Lisa C. Heller ,  Damian L. Osisek ,  Donald W. Schmidt ,  Patrick M. West, JR. ,  Phil C. Yeh

IPC: G06F3/06 ,  G06F13/24 ,  G06F12/0802 ,  G06F12/06 ,  G06F9/30

Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

公开(公告)号：US10360033B2

公开(公告)日：2019-07-23

申请号：US16018343

申请日：2018-06-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dan F. Greiner ,  Christian Jacobi ,  Marcel Mitran ,  Donald W. Schmidt ,  Timothy J. Slegel

IPC: G06F9/30 ,  G06F9/46 ,  G06F9/38

Abstract: A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.

公开(公告)号：US20190050227A1

公开(公告)日：2019-02-14

申请号：US16154231

申请日：2018-10-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles W. Gainey, JR. ,  Dan F. Greiner ,  Christian Jacobi ,  Marcel Mitran ,  Donald W. Schmidt ,  Timothy J. Slegel

IPC: G06F9/30 ,  G06F9/54 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/30021 ,  G06F9/30029 ,  G06F9/3005 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/455 ,  G06F9/542

Abstract: A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.

公开(公告)号：US10120681B2

公开(公告)日：2018-11-06

申请号：US14212378

申请日：2014-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles W. Gainey, Jr. ,  Dan F. Greiner ,  Christian Jacobi ,  Marcel Mitran ,  Donald W. Schmidt ,  Timothy J. Slegel

IPC: G06F9/30 ,  G06F9/54 ,  G06F9/38 ,  G06F9/455

Abstract: A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.

公开(公告)号：US09921849B2

公开(公告)日：2018-03-20

申请号：US14828768

申请日：2015-08-18

Applicant: International Business Machines Corporation

Inventor： Jonathan D. Bradbury ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Dan F. Greiner ,  Lisa Cranton Heller ,  Jeffrey P. Kubala ,  Damian L. Osisek ,  Donald W. Schmidt ,  Timothy J. Slegel

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/5077

Abstract: Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer implemented method for address adjustment in a configuration is provided. The configuration includes a core configurable between an ST mode and an MT mode, where the ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The primary thread is accessed in the ST mode using a core address value. Switching from the ST mode to the MT mode is performed. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value. The expanded address value includes the core address value concatenated with a thread address value.