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1.发明授权公开(公告)号：US11693692B2
公开(公告)日：2023-07-04
申请号：US17350365
申请日：2021-06-17
CPC分类号： G06F9/4812 , G06F9/5016 , G06N3/08
摘要： Instruction processing is performed for an instruction. The instruction is configured to perform a plurality of functions, in which a function of the plurality of functions is to be performed in a plurality of processing phases. A processing phase is defined to store up to a select amount of data. The select amount of data is based on the function to be performed. At least one function of the plurality of functions has a different value for the select amount of data than at least one other function. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of a select function. Based on determining that the store into the designated area occurred, an interrupt is presented, and based on determining that the store into the designated area did not occur, instruction processing is continued.
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公开(公告)号：US20220405101A1
公开(公告)日：2022-12-22
申请号：US17350393
申请日：2021-06-17
发明人： Laith M. AlBarakat , Jonathan D. Bradbury , Timothy Slegel , Cedric Lichtenau , Simon Weishaupt , Anthony Saporito
摘要： A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.
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公开(公告)号：US11531546B2
公开(公告)日：2022-12-20
申请号：US17194740
申请日：2021-03-08
发明人： Eric Mark Schwarz , Stefan Payer , Petra Leber , Kerstin Claudia Schelm , Michael Klein , Timothy Slegel , Reid Copeland , Xin Guo
摘要： An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.
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公开(公告)号：US20210406390A1
公开(公告)日：2021-12-30
申请号：US17469171
申请日：2021-09-08
发明人： Timothy Slegel , Elpida Tzortzatos
摘要： A single architected instruction to perform multiple functions is executed. The executing includes performing a first function of the multiple functions and a second function of the multiple functions. The first function includes moving a block of data from one location to another location, and the second function includes setting one portion of a storage key using one selected key and another portion of the storage key using another selected key. The storage key is associated with the block of data and controls access to the block of data. The first function and the second function are performed as part of the single architected instruction.
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公开(公告)号：US11061685B2
公开(公告)日：2021-07-13
申请号：US16286985
申请日：2019-02-27
发明人： Louis P. Gomes , Bruce Giamei , Timothy Slegel , Mark Farrell , Matthias Klein
摘要： A method is provided that is executable by a processor of a computer. Note that the processor is communicatively coupled to a memory of the computer, and the memory stores a response block of a call command. In implementing the method, the processor defines a sub-functions field in the response block of the call command. Further the processor indicates that a set of functions of a set of instructions are installed and available at an interface based on a corresponding sub-functions flag within the sub-functions field being set. Note that the interface is also being executed on the computer and that the set of functions being represented by the corresponding sub-functions flag. The processor further indicates that the set of functions of the set of instructions are not installed based on the corresponding sub-functions flag not being set.
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公开(公告)号：US10831503B2
公开(公告)日：2020-11-10
申请号：US16182017
申请日：2018-11-06
发明人： Bruce C. Giamei , Martin Recktenwald , Donald W. Schmidt , Timothy Slegel , Aditya N. Puranik , Mark S. Farrell , Christian Jacobi , Jonathan D. Bradbury , Christian Zoellin
摘要： Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.
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公开(公告)号：US10831480B2
公开(公告)日：2020-11-10
申请号：US16283966
申请日：2019-02-25
发明人： Timothy Slegel , Elpida Tzortzatos
摘要： A single architected instruction is obtained to perform multiple functions. The instruction is executed, and the executing includes performing a first function of the multiple functions and a second function of the multiple functions. The first function includes moving a block of data from one location to another location, and the second function includes setting a storage key. The storage key is associated with the block of data at the other location and controls access to the block of data. The first function and the second function are performed as part of the single architected instruction.
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公开(公告)号：US12013791B2
公开(公告)日：2024-06-18
申请号：US17335224
申请日：2021-06-01
发明人： Bruce Conrad Giamei , Timothy Slegel , Christian Borntraeger , Damian Osisek , Lisa Cranton Heller , Ute Gaertner , Christine Michele Yost , Elpida Tzortzatos
IPC分类号： G06F12/1027 , G06F12/02 , G06F12/0891 , G06F12/14
CPC分类号： G06F12/1027 , G06F12/0246 , G06F12/0292 , G06F12/0891 , G06F12/1425
摘要： An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.
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9.发明授权公开(公告)号：US12008395B2
公开(公告)日：2024-06-11
申请号：US18308793
申请日：2023-04-28
CPC分类号： G06F9/4812 , G06F9/5016 , G06N3/08
摘要： Instruction processing is performed for an instruction. The instruction is configured to perform a function, which is to be performed in a plurality of processing phases. A processing phase is defined to store up to a selected amount of data. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of the function. Based on determining that the store into the designated area occurred, an interrupt is presented.
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公开(公告)号：US11809870B2
公开(公告)日：2023-11-07
申请号：US17224373
申请日：2021-04-07
CPC分类号： G06F9/30145 , G06F9/30167 , G06F9/45541 , G06F9/45554
摘要： In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.
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