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公开(公告)号：US11221826B2
公开(公告)日：2022-01-11
申请号：US16525768
申请日：2019-07-30
摘要： Embodiments of the invention are directed to a computer-implemented method of for parallel conversion to binary coded decimal format. The method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value. The FPU receives the rounding information and operates on the BCD value accordingly.
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公开(公告)号：US11042371B2
公开(公告)日：2021-06-22
申请号：US16567398
申请日：2019-09-11
摘要： A method for detecting faults in substring search operations includes providing, using a processor unit including vector registers of M vector elements each, an M×M matrix of comparators for characterwise comparison of the elements of a reference string stored in a first one of the vector registers and a target string stored in a second one of the vector registers. A vector element is an n-bit element for encoding a character. A resulting bit vector is generated using comparison performed by the M×M matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicates characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by utilizing the resulting bit vector.
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3.发明授权公开(公告)号：US10996951B2
公开(公告)日：2021-05-04
申请号：US16567356
申请日：2019-09-11
IPC分类号： G06F9/30
摘要： A method for detecting faults in substring search operations using a processor unit including vector registers of M vector elements each. A non-limiting example of the method includes providing an M×M matrix of comparators for characterwise comparison of the elements of a reference string and a target string. A first zero detect vector having value indicative of terminating element of the target string and a second zero detect vector having a value indicative of terminating element of the reference string are generated. A resulting bit vector is generated using comparison performed by the M×M matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicate characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by comparing the generated zero detect vectors with operands.
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公开(公告)号：US20200341839A1
公开(公告)日：2020-10-29
申请号：US16397107
申请日：2019-04-29
发明人： Stefan Payer , Michael Klein , Nicol Hofmann , Cedric Lichtenau
摘要： Aspects include parsing, by a computer system, a design file of an integrated circuit including a plurality of stages to extract a plurality of inputs and outputs of a plurality of latches. The computer system can sort the latches based on latch locations in the stages and build a plurality of ordered vectors of signals before and after the latches based on the sorting. The computer system can build a plurality of parity vectors for each of the ordered vectors of signals before and after the latches, build a latch bank for each of the parity vectors before the latches, and build a parity vector comparison to detect a parity failure based on comparing the parity vectors after the latches with an output of the latch bank.
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公开(公告)号：US10732972B2
公开(公告)日：2020-08-04
申请号：US16109840
申请日：2018-08-23
IPC分类号： G06F9/30 , G06F16/903
摘要： A number of non-overlapping instances of a substring occurring within a string of data elements can be determined through a method that includes partitioning and distributing the string to an ordered list of equal length segments that each have a length greater or equal to L. A substring match within a target segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. It can be subsequently determined that the target segment contains additional data elements, and a new segment can be generated by clearing L−1 data elements following a position of the substring match in the target segment. An additional substring match can be detected by comparing the substring with the new segment.
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公开(公告)号：US09977680B2
公开(公告)日：2018-05-22
申请号：US15282077
申请日：2016-09-30
CPC分类号： G06F9/3869 , G06F1/3237 , G06F1/3287
摘要： A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.
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7.发明公开公开(公告)号：US20230289138A1
公开(公告)日：2023-09-14
申请号：US17653946
申请日：2022-03-08
发明人： Petra Leber , Kerstin Claudia Schelm , Cedric Lichtenau , Stefan Payer , Michael Klein , Silvia Melitta Mueller
IPC分类号： G06F7/48
CPC分类号： G06F7/48
摘要： A hardware device is provided to perform a plurality of operations to convert an input value directly from one format to another format. The hardware device is to perform the plurality of operations based on execution of an instruction. The plurality of operations includes scaling the input value to provide a scaled result and converting the scaled result from the one format to provide a converted result in the other format. The scaling and converting are to be performed as part of executing the instruction. The converted result in the other format is provided to be used in processing within the computing environment.
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公开(公告)号：US11099602B2
公开(公告)日：2021-08-24
申请号：US16398793
申请日：2019-04-30
摘要： A method includes obtaining a trigger signal directed to a component in a subset of components of an electronic circuit, and activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal. An active period is determined based on the trigger signal. The clock remains active for the active period. One of a timer or counter is initiated for the active period. A limit is defined for the one of the timer or counter. The active period is dynamically extended for a busy period after the one of the timer or counter is initiated. The clock is deactivated following the active period.
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公开(公告)号：US11068541B2
公开(公告)日：2021-07-20
申请号：US16276712
申请日：2019-02-15
IPC分类号： G06F7/00 , G06F16/903 , G06F40/205 , G06F17/16
摘要： An instruction is provided for performing a vector string search. The instruction to be processed is obtained, with the instruction being defined to be a string search instruction to locate occurrence of a substring within a string. The instruction is processed, with the processing including searching the string specified in one operand of the instruction using the substring specified in another operand of the instruction. Based on the searching locating a first full match of the substring within the string, a full match condition indication is returned with position of the first full match in the string, and based on the searching locating only a partial match of the substring at a termination of the string, a partial match condition indication is returned, with the position of the partial match in the string.
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公开(公告)号：US10169451B1
公开(公告)日：2019-01-01
申请号：US15957984
申请日：2018-04-20
IPC分类号： H03K19/173 , G06F17/30 , H03K19/177 , G06F17/16 , G06F9/30 , H03K19/20
摘要： A processor unit can be used to rapidly search a string of characters. The processor unit can include vector registers each having M vector elements, each vector element having n bits of data for containing an encoded character. An M×M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each diagonal of the matrix of comparators, and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. Correction logic within the processor unit can suppress indications of a partial match or of a full match in the bit vector.
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