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公开(公告)号：US11531546B2
公开(公告)日：2022-12-20
申请号：US17194740
申请日：2021-03-08
发明人： Eric Mark Schwarz , Stefan Payer , Petra Leber , Kerstin Claudia Schelm , Michael Klein , Timothy Slegel , Reid Copeland , Xin Guo
摘要： An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.
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公开(公告)号：US10558432B2
公开(公告)日：2020-02-11
申请号：US15856255
申请日：2017-12-28
摘要： Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.
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公开(公告)号：US10310815B1
公开(公告)日：2019-06-04
申请号：US15827761
申请日：2017-11-30
摘要： A method to produce a final product from a multiplicand and a multiplier is provided. The method is executed by a parallel decimal multiplication hardware architecture, which includes a 3× generator, at least one additional generator, a multiplier recoder, a partial product tree, and a decimal adder. The 3× generator, the at least one additional generator, and the multiplier recoder generate decimal partial products from the multiplicand and the multiplier. The partial product tree executes a reduction of the decimal partial products to produce two corresponding partial product accumulations. The decimal adder adds the two corresponding partial product accumulations of the decimal partial products to produce the final product.
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公开(公告)号：US20190018655A1
公开(公告)日：2019-01-17
申请号：US15897472
申请日：2018-02-15
摘要： Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.
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公开(公告)号：US20190018654A1
公开(公告)日：2019-01-17
申请号：US15856255
申请日：2017-12-28
摘要： Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.
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公开(公告)号：US10140090B2
公开(公告)日：2018-11-27
申请号：US15278206
申请日：2016-09-28
发明人： Michael Klein , Manuela Niekisch
IPC分类号： G06F7/44
摘要： Methods, systems and computer program products for computing and summing up multiple products in a single multiplier are provided. Aspects include receiving a first number and a second number, creating partial products of the first number and the second number based on a multiplication of the first number and the second number, and reducing the number of partial products to create an intermediate result. Aspects also include receiving a third number and a fourth number, creating partial products of the third number and the fourth number based on a multiplication of the third number and the fourth number, creating a reduction tree and adding the intermediate result to the reduction tree. Aspects further include reducing the number of partial products in the reduction tree to create a second sum value and a second carry value and adding the second sum value and the second carry value to create a result.
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公开(公告)号：US20180088905A1
公开(公告)日：2018-03-29
申请号：US15278206
申请日：2016-09-28
发明人： Michael Klein , Manuela Niekisch
IPC分类号： G06F7/44
CPC分类号： G06F7/443 , G06F7/5275 , G06F2207/38
摘要： Methods, systems and computer program products for computing and summing up multiple products in a single multiplier are provided. Aspects include receiving a first number and a second number, creating partial products of the first number and the second number based on a multiplication of the first number and the second number, and reducing the number of partial products to create an intermediate result. Aspects also include receiving a third number and a fourth number, creating partial products of the third number and the fourth number based on a multiplication of the third number and the fourth number, creating a reduction tree and adding the intermediate result to the reduction tree. Aspects further include reducing the number of partial products in the reduction tree to create a second sum value and a second carry value and adding the second sum value and the second carry value to create a result.
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公开(公告)号：US20170220318A1
公开(公告)日：2017-08-03
申请号：US15011735
申请日：2016-02-01
CPC分类号： G06F7/4876 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/485 , G06F7/5443 , G06F2207/483
摘要： A binary fused multiply-add floating-point unit configured to operate on an addend, a multiplier, and a multiplicand. The unit is configured to receive as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path; to perform an alignment shift of the unrounded addend on an unrounded exponent and an unrounded mantissa; as well as perform a rounding correction for the addend in parallel to the actual alignment shift, responsive to a rounding-up signal.
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公开(公告)号：US11861325B2
公开(公告)日：2024-01-02
申请号：US17480180
申请日：2021-09-21
CPC分类号： G06F5/012 , G06F7/49947 , G06F2207/3844
摘要： A method includes dividing a fraction of a floating point result into a first portion and a second portion. The method includes outputting a first normalizer result based on the first portion during to a first clock cycle. The method includes storing a first segment of the first portion during to the first clock cycle. The method includes outputting a first rounder result based on the first normalizer result during to the first clock cycle. The method includes outputting a second normalizer result based on the second portion during to a second clock cycle. The method includes outputting a second rounder result based on the second normalizer result and the first segment during to the second clock cycle.
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10.发明公开公开(公告)号：US20230289138A1
公开(公告)日：2023-09-14
申请号：US17653946
申请日：2022-03-08
发明人： Petra Leber , Kerstin Claudia Schelm , Cedric Lichtenau , Stefan Payer , Michael Klein , Silvia Melitta Mueller
IPC分类号： G06F7/48
CPC分类号： G06F7/48
摘要： A hardware device is provided to perform a plurality of operations to convert an input value directly from one format to another format. The hardware device is to perform the plurality of operations based on execution of an instruction. The plurality of operations includes scaling the input value to provide a scaled result and converting the scaled result from the one format to provide a converted result in the other format. The scaling and converting are to be performed as part of executing the instruction. The converted result in the other format is provided to be used in processing within the computing environment.
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