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    Memory safety interface configuration
    1.
    发明授权
    Memory safety interface configuration 有权

    公开(公告)号：US12038812B2

    公开(公告)日：2024-07-16

    申请号：US17839379

    申请日：2022-06-13

    申请人： Synopsys, Inc.

    发明人： Adrianus Wilhelmus Petrus Gerardus Gertruda Vaassen

    IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F12/02

    CPC分类号： G06F11/141 ,  G06F12/02 ,  G06F2201/805 ,  G06F2212/251

    摘要： A memory safety interface module (MSIM) configured to test a memory. The MSIM receives an original data from a digital logic and inverts the bits of the original data to generate an inverted data. It writes the inverted data to the memory address. The MSIM reads the inverted data from the memory address and determines whether the memory address and the inverted data are correct. The MSIM either writes the original data to the memory address in response to the memory address and the inverted data being correct or transmits an error indication in response to at least one of the memory address and the inverted data being incorrect. The MSIM reads the original data from the memory address and determines whether the memory address and the original data are correct or transmits an error indication in response to at least one of the memory address and the original data being incorrect.

    MEMORY CONTROLLER PERFORMING ERROR CORRECTION AND OPERATING METHOD THEREOF
    2.
    发明公开
    MEMORY CONTROLLER PERFORMING ERROR CORRECTION AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240211345A1

    公开(公告)日：2024-06-27

    申请号：US18349712

    申请日：2023-07-10

    申请人： SK hynix Inc.

    发明人： Jae Yong SON ,  Dae Sung KIM ,  Min Su CHOI

    IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/14

    CPC分类号： G06F11/1068 ,  G06F11/0772 ,  G06F11/141

    摘要： A memory device may include a read controller and an error correction circuit. The read controller may sequentially perform a plurality of read retry operations on a memory device. The error correction circuit may perform a plurality of first error correction decodings on read data respectively acquired from the plurality of read retry operations, store a plurality of Unsatisfied Syndrome Check (USC) values respectively produced by the plurality of first error correction decodings, and perform a second error correction decoding based on read data corresponding to a minimum USC value among the plurality of USC values.

    STORAGE DEVICE AND STORAGE SYSTEM
    4.
    发明公开
    STORAGE DEVICE AND STORAGE SYSTEM 审中-公开

    公开(公告)号：US20240045765A1

    公开(公告)日：2024-02-08

    申请号：US18348713

    申请日：2023-07-07

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jungsoo Kim ,  Dongouk Moon ,  Kyungkeun Lee

    IPC分类号： G06F11/14 ,  G06F11/30

    CPC分类号： G06F11/141 ,  G06F11/1441 ,  G06F11/3037

    摘要： Provided is a storage device including a non-volatile memory, a memory controller configured to communicate with a host device through a first channel and configured to control the non-volatile memory, and a sub controller configured to communicate with the host device through a second channel and configured to monitor an operation status of the memory controller. The sub controller is configured to perform operations including broadcasting state information of the storage device including the operation status to at least one external device through the second channel, and performing a recovery operation on the memory controller when recovery information is received from the at least one external device through the second channel.

    Triple modular redundancy (TMR) radiation hardened memory system
    5.
    发明授权
    Triple modular redundancy (TMR) radiation hardened memory system 有权

    公开(公告)号：US11861181B1

    公开(公告)日：2024-01-02

    申请号：US17818850

    申请日：2022-08-10

    申请人： BAE SYSTEMS Information and Electronic Systems Integration Inc.

    发明人： David D. Moser ,  Richard J. Ferguson ,  Daniel L. Stanley

    IPC分类号： G06F11/07 ,  G06F3/06 ,  G06F11/14

    CPC分类号： G06F3/0619 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/0772 ,  G06F11/141

    摘要： Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.