公开(公告)号：US20240029787A1

公开(公告)日：2024-01-25

申请号：US18063007

申请日：2022-12-07

Applicant: SK hynix Inc.

Inventor： Jae Yong SON ,  Nam Kyeong KIM ,  Hoon CHO ,  Hyuk Min KWON ,  Dae Sung KIM ,  Jang Seob KIM ,  Sang Ho YUN

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4078

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4078

Abstract: A storage device includes a memory including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, and a controller configured to control the memory and perform a read retry operation for the memory using a read retry table. The memory includes a special block that stores a read retry table in which a plurality of read retry values are set for each of a plurality of first conditions and each of a plurality of second conditions corresponding to each of the plurality of first conditions.

公开(公告)号：US20250131969A1

公开(公告)日：2025-04-24

申请号：US18604519

申请日：2024-03-14

Applicant: SK hynix Inc.

Inventor： Jae Yong SON ,  Jeong Myung LEE

IPC: G11C29/02 ,  G11C29/52

Abstract: A read retry table generator is coupled to a plurality of memory dies via a data path. The read retry table generator is configured to: collect data from a plurality of memory cells coupled to a plurality of word lines in the plurality of memory dies; determine a pass rate of collected data appertaining to a plurality of clusters; select a cluster candidate among the plurality of clusters, based on a pass rate of collected data; and cluster the collected data into the cluster candidate to generate a read retry table.

公开(公告)号：US20240320075A1

公开(公告)日：2024-09-26

申请号：US18462290

申请日：2023-09-06

Applicant: SK hynix Inc.

Inventor： Jae Yong SON

IPC: G06F11/07 ,  G11C16/26

CPC classification number: G06F11/076 ,  G11C16/26

Abstract: A semiconductor storage device searches for an optimal read voltage on the basis of an error bit variance for each second read voltage interval without performing repeated additional reads up to the limit of left and right cell difference probabilities. Accordingly, the semiconductor storage device can detect an optimal read voltage rapidly and accurately by minimizing the number of reads for a memory cell, when performing a second read for determining the optimal read voltage.

公开(公告)号：US20240404618A1

公开(公告)日：2024-12-05

申请号：US18531227

申请日：2023-12-06

Applicant: SK hynix Inc.

Inventor： Jae Yong SON

IPC: G11C29/50 ,  G11C7/20 ,  G11C29/12

Abstract: A data clustering system includes: an initialization circuit configured to receive a data set including a plurality of samples and a number K of groups, where K is a natural number, and determine at least a part number of initial centroids based on frequency of a data value of the sample, wherein the number of initial centroids corresponds to the number K of groups; and a classification circuit configured to group the plurality of samples based on a distance between the data value corresponding to the sample and each of centroids.

公开(公告)号：US20240211345A1

公开(公告)日：2024-06-27

申请号：US18349712

申请日：2023-07-10

Applicant: SK hynix Inc.

Inventor： Jae Yong SON ,  Dae Sung KIM ,  Min Su CHOI

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/141

Abstract: A memory device may include a read controller and an error correction circuit. The read controller may sequentially perform a plurality of read retry operations on a memory device. The error correction circuit may perform a plurality of first error correction decodings on read data respectively acquired from the plurality of read retry operations, store a plurality of Unsatisfied Syndrome Check (USC) values respectively produced by the plurality of first error correction decodings, and perform a second error correction decoding based on read data corresponding to a minimum USC value among the plurality of USC values.

公开(公告)号：US20250130717A1

公开(公告)日：2025-04-24

申请号：US18597949

申请日：2024-03-07

Applicant: SK hynix Inc.

Inventor： Jae Yong SON ,  Hong Sik YUN

IPC: G06F3/06

Abstract: An embodiment of the present disclosure may provide a read retry table optimized for a memory on the basis of a distribution of read voltages of word lines included in the corresponding memory, and by changing a method of setting a read retry table depending on the number of sample data, may provide an optimal read retry table even for a memory with insufficient sample data.

公开(公告)号：US20240355405A1

公开(公告)日：2024-10-24

申请号：US18469562

申请日：2023-09-19

Applicant: SK hynix Inc.

Inventor： Jae Yong SON ,  Nam Kyeong KIM

IPC: G11C29/12 ,  G11C29/18 ,  G11C29/42

CPC classification number: G11C29/1201 ,  G11C29/18 ,  G11C29/42 ,  G11C2029/1202

Abstract: A read retry table (RRT) apparatus is coupled to a plurality of memory dies via a data path. The apparatus is configured to collect data from a plurality of memory cells coupled to a plurality of word lines in the plurality of memory dies via the data path; perform a first clustering on the plurality of word lines based on an error correction capability of error correction circuitry for collected data; perform a second clustering on an outlier of the first clustering; and generate or update an RRT based on values obtained from the first clustering and the second clustering.

公开(公告)号：US20240281321A1

公开(公告)日：2024-08-22

申请号：US18447326

申请日：2023-08-10

Applicant: SK hynix Inc.

Inventor： Jae Yong SON ,  Dae Sung KIM ,  Min Su CHOI

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: Provided herein may be a memory controller and a memory system including the same. The memory controller may include an error correction circuit configured to perform error correction decoding on data that is read by read retry operations, a buffer memory configured to store decoding history information including retry fail voltages used for a failure in the read retry operations and syndrome weights respectively corresponding to the retry fail voltages, and a processor configured to, when a number of times that the read retry operations fail reaches a threshold number of times, determine a voltage corresponding to a minimum syndrome weight determined based on a relationship between changes in the syndrome weights relative to magnitudes of the retry fail voltages, to be an optimally estimated read voltage, and provide data that is read using the optimally estimated read voltage to the error correction circuit.