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    DIRECTED INTERRUPT VIRTUALIZATION WITH BLOCKING INDICATOR
    3.
    发明申请
    DIRECTED INTERRUPT VIRTUALIZATION WITH BLOCKING INDICATOR 审中-公开

    公开(公告)号：US20200264995A1

    公开(公告)日：2020-08-20

    申请号：US16789567

    申请日：2020-02-13

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Christoph Raisch ,  Marco Kraemer ,  Donald William Schmidt ,  Bernd Nerz ,  Sascha Junghans ,  Peter Dana Driever

    IPC: G06F13/24 ,  G06F9/48 ,  G06F9/455 ,  G06F12/1009

    Abstract: An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is blocked from receiving interrupt signals using an interrupt blocking indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor unblocked, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

    Management of data transaction from I/O devices
    4.
    发明授权
    Management of data transaction from I/O devices 有权

    公开(公告)号：US10223307B2

    公开(公告)日：2019-03-05

    申请号：US15623429

    申请日：2017-06-15

    Applicant: International Business Machines Corporation

    Inventor： David F. Craddock ,  Sascha Junghans ,  Matthias Klein ,  Eric N. Lais

    IPC: G06F13/28 ,  G06F13/42 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/1081

    Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

    PREINSTALL OF PARTIAL STORE CACHE LINES
    5.
    发明申请
    PREINSTALL OF PARTIAL STORE CACHE LINES 审中-公开

    公开(公告)号：US20180374522A1

    公开(公告)日：2018-12-27

    申请号：US15629923

    申请日：2017-06-22

    Applicant: International Business Machines Corporation

    Inventor： Ekaterina M. Ambroladze ,  Sascha Junghans ,  Matthias Klein ,  Pak-Kin Mak ,  Robert J. Sonnelitter, III ,  Chad G. Wilson

    IPC: G11C8/06 ,  G06F3/06 ,  G06F13/16

    Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

    Systems and methods for accessing cache memory
    6.
    发明授权
    Systems and methods for accessing cache memory 有权
    访问高速缓存的系统和方法

    公开(公告)号：US09384131B2

    公开(公告)日：2016-07-05

    申请号：US13843278

    申请日：2013-03-15

    Applicant: International Business Machines Corporation

    Inventor： Christian Habermann ,  Christian Jacobi ,  Sascha Junghans ,  Martin Recktenwald ,  Hans-Werner Tast

    IPC: G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/1024

    Abstract: Systems and methods for providing data from a cache memory to requestors includes a number of cache memory levels arranged in a hierarchy. The method includes receiving a request for fetching data from the cache memory and determining one or more addresses in a cache memory level which is one level higher than a current cache memory level using one or more prediction algorithms. Further, the method includes pre-fetching the one or more addresses from the high cache memory level and determining if the data is available in the addresses. If data is available in the one or more addresses then data is fetched from the high cache level, else addresses of a next level which is higher than the high cache memory level are determined and pre-fetched. Furthermore, the method includes providing the fetched data to the requestor.

    Abstract translation: 用于从缓存存储器向请求者提供数据的系统和方法包括以层级布置的多个高速缓存存储器级。 该方法包括从高速缓冲存储器接收数据取出请求，并使用一个或多个预测算法确定高于当前高速缓存存储器级别的一级的高速缓冲存储器级别中的一个或多个地址。 此外，该方法包括从高速缓冲存储器级别预取一个或多个地址，并确定该地址中的数据是否可用。 如果数据在一个或多个地址中可用，则从高高速缓存级别获取数据，否则确定并预取高于高缓存存储器级别的下一级的地址。 此外，该方法包括将提取的数据提供给请求者。

    TRACING DATA FROM AN ASYNCHRONOUS INTERFACE
    9.
    发明申请
    TRACING DATA FROM AN ASYNCHRONOUS INTERFACE 有权
    从非同步接口追踪数据

    公开(公告)号：US20150365225A1

    公开(公告)日：2015-12-17

    申请号：US14733249

    申请日：2015-06-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC: H04L7/02 ,  H04L7/00

    CPC classification number: G06F11/348 ,  G06F11/3027 ,  G06F11/349 ,  G06F2201/86 ,  H04L7/0045 ,  H04L7/02

    Abstract: An apparatus for tracing data from a data bus in a first clock domain operating at a first clock frequency to a trace array in a second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency. The apparatus includes a change detector to detect a change of the data on the data bus in the first clock domain, a trigger responsive to the change detector to send a trigger pulse to the second clock domain, pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch, as well as a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.

    Abstract translation: 一种用于在以第一时钟频率操作的第一时钟域中的数据总线跟踪数据到在第二时钟频率下操作的第二时钟域中的跟踪阵列的装置，其中所述第一时钟频率低于所述第二时钟频率。 该装置包括：变化检测器，用于检测在第一时钟域中的数据总线上的数据的变化;触发响应于变化检测器的触发信号以向第二时钟域发送触发脉冲，响应于第二时钟域的脉冲同步 所述触发脉冲通过元稳定性锁存器将所述触发脉冲与所述第二时钟域的所述第二时钟频率同步，以及响应于所述脉冲同步以从所述数据总线捕获数据的所述第二时钟域中的数据捕获，以及 将捕获的数据存储在跟踪数组中。

    Write and read collision avoidance in single port memory devices
    10.
    发明授权
    Write and read collision avoidance in single port memory devices 有权
    在单端口存储设备中写入和读取冲突避免

    公开(公告)号：US08995210B1

    公开(公告)日：2015-03-31

    申请号：US14090060

    申请日：2013-11-26

    Applicant: International Business Machines Corporation

    Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/1015 ,  G11C7/1075 ,  G11C2207/2209

    Abstract: A method of avoiding a write collision in single port memory devices from two or more independent write operations is described. A first write operation having a first even data object and a first odd data object is received from a first data sender. A second write operation having a second even data object and a second odd data object is received from a second data sender at substantially the same time as the first write operation. The second write operation is delayed so that the first even data object writes to a first single port memory device at a different time than the second even data object writes to the first single port memory device. The second write operation is delayed so that the first odd data object writes to a second single port memory device at a different time than the second odd data object.

    Abstract translation: 描述了避免来自两个或多个独立写入操作的单端口存储器件中的写入冲突的方法。 从第一数据发送器接收具有第一偶数数据对象和第一奇数数据对象的第一写操作。 在与第一写入操作基本相同的时间，从第二数据发送器接收具有第二偶数数据对象和第二奇数数据对象的第二写操作。 第二写操作被延迟，使得第一偶数数据对象以与第二偶数数据对象写入第一单端口存储器设备不同的时间写入第一单端口存储器设备。 第二写操作被延迟，使得第一奇数数据对象在与第二奇数数据对象不同的时间写入第二单端口存储器件。

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