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1.发明申请公开(公告)号：US20180307628A1
公开(公告)日：2018-10-25
申请号：US15496525
申请日：2017-04-25
发明人： Michael A. Blake , Pak-kin Mak , Robert J. Sonnelitter, III , Timothy W. Steele , Gary E. Strait , Poornima P. Sulibele , Guy G. Tracy
IPC分类号： G06F12/14 , G06F12/0891 , G06F13/40
CPC分类号： G06F12/1466 , G06F12/0891 , G06F13/4036 , G06F2212/1052
摘要： A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.
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公开(公告)号：US20160124653A1
公开(公告)日：2016-05-05
申请号：US14946015
申请日：2015-11-19
发明人： Ekaterina M. Ambroladze , Garrett M. Drapala , Norbert Hagspiel , Sascha Junghans , Matthias Klein , Gary E. Strait
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F3/0647 , G06F3/0683 , G06F12/0842 , G06F13/4221 , G06F2212/271 , G06F2212/604
摘要： A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.
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公开(公告)号：US20150261569A1
公开(公告)日：2015-09-17
申请号：US14208257
申请日：2014-03-13
发明人： Deanna Postles Dunn Berger , Kathryn M. Jackson , Joshua D. Massover , Gary E. Strait , Hanno Ulrich , Craig R. Walters
IPC分类号： G06F9/48
CPC分类号： G06F9/4881 , G06F11/30 , G06F11/3024 , G06F11/3055 , G06F11/3409 , G06F11/3476 , G06F11/348
摘要： Embodiments are directed to systems and methodologies for efficiently sampling data for analysis by a pipeline analysis algorithm. The amount of sampled data is maximized without increasing sampling overhead by sampling “non-pipeline activity” data if the subject pipeline is inactive during the sampling time. The non-pipeline activity data is selected to include overall system information that is relevant to the subject pipeline's performance but is not necessarily dependent on whether the subject pipeline is active. In some embodiments, the non-pipeline activity data allows for confirmation of a pipeline performance characteristic that must otherwise be inferred by the subsequent pipeline analysis algorithm from data sampled while the pipeline was active. In some embodiments, the non-pipeline activity data allows the pipeline analysis algorithm to analyze additional performance characteristics that cannot otherwise be inferred from the data sampled while the pipeline was active.
摘要翻译： 实施例涉及用于通过流水线分析算法有效地采样数据进行分析的系统和方法。 如果在采样时间内主体管线不活动，则采样数据的数量最大化，而不会通过采样“非流水线活动”数据而增加采样开销。 选择非流水线活动数据以包括与主体管线的性能相关的整体系统信息，但不一定取决于主体流水线是否活动。 在一些实施例中，非流水线活动数据允许确认流水线性能特征，否则在流水线活动时，必须由随后的流水线分析算法从采样的数据中推断。 在一些实施例中，非流水线活动数据允许流水线分析算法分析在流水线处于活动状态时所采样的数据不能被推断的附加性能特征。
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公开(公告)号：US20160217077A1
公开(公告)日：2016-07-28
申请号：US14606432
申请日：2015-01-27
发明人： Ekaterina M. Ambroladze , Timothy C. Bronson , Garrett M. Drapala , Michael Fee , Matthias Klein , Pak-kin Mak , Robert J. Sonnelitter, III , Gary E. Strait
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F12/0833 , G06F2212/1021 , G06F2212/608 , G06F2212/621
摘要： Maintaining store order with high throughput in a distributed shared memory system. A request is received for a first ordered data store and a coherency check is initiated. A signal is sent that pipelining of a second ordered data store can be initiated. If a delay condition is encountered during the coherency check for the first ordered data store, rejection of the first ordered data store is signaled. If a delay condition is not encountered during the coherency check for the first ordered data store, a signal is sent indicating a readiness to continue pipelining of the second ordered data store.
摘要翻译： 在分布式共享存储器系统中维护具有高吞吐量的存储顺序。 接收到针对第一有序数据存储的请求，并且启动一致性检查。 发送信号，可以启动第二个有序数据存储的流水线。 如果在第一有序数据存储器的一致性检查期间遇到延迟条件，则发信号通知第一有序数据存储器的拒绝。 如果在第一有序数据存储器的一致性检查期间没有遇到延迟条件，则发送指示准备继续流水线化第二有序数据存储的信号。
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公开(公告)号：US09268660B2
公开(公告)日：2016-02-23
申请号：US14205910
申请日：2014-03-12
发明人： Garrett M. Drapala , Gary E. Strait
IPC分类号： G06F11/273 , G11C29/12 , G11C29/40 , G11C29/04
摘要： Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.
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公开(公告)号：US10572304B2
公开(公告)日：2020-02-25
申请号：US14501190
申请日：2014-09-30
发明人： Deanna Postles Dunn Berger , Kathryn M. Jackson , Joshua D. Massover , Gary E. Strait , Hanno Ulrich , Craig R. Walters
摘要： Embodiments are directed to methodologies for efficiently sampling data for analysis by a pipeline analysis algorithm. The amount of sampled data is maximized without increasing sampling overhead by sampling “non-pipeline activity” data if the subject pipeline is inactive during the sampling time. The non-pipeline activity data is selected to include overall system information that is relevant to the subject pipeline's performance but is not necessarily dependent on whether the subject pipeline is active. In some embodiments, the non-pipeline activity data allows for confirmation of a pipeline performance characteristic that must otherwise be inferred by the subsequent pipeline analysis algorithm from data sampled while the pipeline was active. In some embodiments, the non-pipeline activity data allows the pipeline analysis algorithm to analyze additional performance characteristics that cannot otherwise be inferred from the data sampled while the pipeline was active.
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公开(公告)号：US20150260792A1
公开(公告)日：2015-09-17
申请号：US14205910
申请日：2014-03-12
发明人： Garrett M. Drapala , Gary E. Strait
IPC分类号： G01R31/317 , G01R31/3177
摘要： Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.
摘要翻译： 实施例涉及基于矩阵和基于压缩的错误检测。 一个方面包括由第一压缩器的第一多个求和模块中的每一个相加矩阵的相应行，所述矩阵包括被测电路的多行和多列输出位，其中每个输出位 被测电路包括矩阵的元素，并且是与行正交的列的行的成员。 另一方面包括由第二压缩器的第二多个求和模块中的每一个相加矩阵的相应输出位列。 另一方面包括基于第一压缩机的输出和第二压缩机的输出中的至少一个来确定被测电路中的误差的存在。
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公开(公告)号：US09299456B2
公开(公告)日：2016-03-29
申请号：US14501676
申请日：2014-09-30
发明人： Garrett M. Drapala , Gary E. Strait
摘要： Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.
摘要翻译： 实施例涉及基于矩阵和基于压缩的错误检测。 一个方面包括由第一压缩器的第一多个求和模块中的每一个相加矩阵的相应行，所述矩阵包括被测电路的多行和多列输出位，其中每个输出位 被测电路包括矩阵的元素，并且是与行正交的列的行的成员。 另一方面包括由第二压缩器的第二多个求和模块中的每一个相加矩阵的相应输出位列。 另一方面包括基于第一压缩机的输出和第二压缩机的输出中的至少一个来确定被测电路中的误差的存在。
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公开(公告)号：US11221795B2
公开(公告)日：2022-01-11
申请号：US16284412
申请日：2019-02-25
IPC分类号： G06F3/06
摘要： Methods, systems, and computer program products for queue management are provided. Aspects include receiving a first queue entry and storing the first queue entry in a queue at a first location, wherein the first queue entry includes a first target destination, receiving a second queue entry and storing the second queue entry in the queue at a second location, wherein the second queue entry includes a second target destination, tracking a relative age for each of the first queue entry and the second queue entry, transmitting the first queue entry to the first target destination based at least in part on the relative age for the first queue entry being greater than the relative age for the second queue entry, and receiving a third queue entry and storing the third queue entry in the queue at the first location.
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公开(公告)号：US20200272357A1
公开(公告)日：2020-08-27
申请号：US16284412
申请日：2019-02-25
IPC分类号： G06F3/06
摘要： Methods, systems, and computer program products for queue management are provided. Aspects include receiving a first queue entry and storing the first queue entry in a queue at a first location, wherein the first queue entry includes a first target destination, receiving a second queue entry and storing the second queue entry in the queue at a second location, wherein the second queue entry includes a second target destination, tracking a relative age for each of the first queue entry and the second queue entry, transmitting the first queue entry to the first target destination based at least in part on the relative age for the first queue entry being greater than the relative age for the second queue entry, and receiving a third queue entry and storing the third queue entry in the queue at the first location.
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