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    Matrix and compression-based error detection
    2.
    发明授权
    Matrix and compression-based error detection 有权
    基于矩阵和基于压缩的错误检测

    公开(公告)号：US09299456B2

    公开(公告)日：2016-03-29

    申请号：US14501676

    申请日：2014-09-30

    Applicant: International Business Machines Corporation

    Inventor： Garrett M. Drapala ,  Gary E. Strait

    IPC: G11C29/04 ,  G11C29/12 ,  G11C29/40 ,  G06F11/273 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52

    CPC classification number: G11C29/04 ,  G06F11/273 ,  G11C29/12 ,  G11C29/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52

    Abstract: Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.

    Abstract translation: 实施例涉及基于矩阵和基于压缩的错误检测。 一个方面包括由第一压缩器的第一多个求和模块中的每一个相加矩阵的相应行，所述矩阵包括被测电路的多行和多列输出位，其中每个输出位 被测电路包括矩阵的元素，并且是与行正交的列的行的成员。 另一方面包括由第二压缩器的第二多个求和模块中的每一个相加矩阵的相应输出位列。 另一方面包括基于第一压缩机的输出和第二压缩机的输出中的至少一个来确定被测电路中的误差的存在。

    NON-DATA INCLUSIVE COHERENT (NIC) DIRECTORY FOR CACHE
    3.
    发明申请
    NON-DATA INCLUSIVE COHERENT (NIC) DIRECTORY FOR CACHE 有权
    非数据包含CACHE的内容（NIC）目录

    公开(公告)号：US20140258621A1

    公开(公告)日：2014-09-11

    申请号：US13784958

    申请日：2013-03-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Rebecca M. Gott ,  Pak-Kin Mak ,  Vijayalakshmi Srinivasan ,  Craig R. Walters

    IPC: G06F12/08

    CPC classification number: G06F12/0833 ,  G06F12/0811 ,  G06F12/0831 ,  G06F2212/283 ,  G06F2212/621

    Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.

    Abstract translation: 实施例涉及用于计算机的对称多处理器（SMP）的非数据包含的一致（NIC）目录。 一个方面包括确定SMP的第一处理器节点的多级高速缓存结构中的最高级缓存的第一逐出条目。 另一方面包括确定NIC目录未满。 另一方面包括确定最高级别高速缓存的第一驱逐条目是由多级缓存结构中的较低级别高速缓存所拥有的。 另一方面包括，基于NIC目录不是完整的，并且基于由较低级别高速缓存所拥有的最高级缓存的第一次驱逐条目，将最高级别高速缓存的第一次驱逐条目的地址安装在 NIC目录中的第一个新条目。 另一方面包括使最高级缓存中的第一个逐出条目无效。

    GRANTING EXCLUSIVE CACHE ACCESS USING LOCALITY CACHE COHERENCY STATE
    6.
    发明申请
    GRANTING EXCLUSIVE CACHE ACCESS USING LOCALITY CACHE COHERENCY STATE 有权

    公开(公告)号：US20160110288A1

    公开(公告)日：2016-04-21

    申请号：US14846875

    申请日：2015-09-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Pak-kin Mak ,  Vesselina K. Papazova ,  Hanno Ulrich

    IPC: G06F12/08

    CPC classification number: G06F12/0815 ,  G06F12/0813 ,  G06F12/0835 ,  G06F12/1416 ,  G06F2212/314 ,  G06F2212/50 ,  G06F2212/621 ,  G06F2212/622

    Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line. The determining being independent of transmission of information relating to the cache line from one or more other nodes of the one or more other regions of nodes.

    EARLY SHARED RESOURCE RELEASE IN SYMMETRIC MULTIPROCESSING COMPUTER SYSTEMS
    9.
    发明申请
    EARLY SHARED RESOURCE RELEASE IN SYMMETRIC MULTIPROCESSING COMPUTER SYSTEMS 有权
    在对称多媒体计算机系统中早期共享资源释放

    公开(公告)号：US20160239418A1

    公开(公告)日：2016-08-18

    申请号：US14621460

    申请日：2015-02-13

    Applicant: International Business Machines Corporation

    Inventor： Garrett M. Drapala ,  Vesselina K. Papazova ,  Robert J. Sonnelitter, III

    IPC: G06F12/08

    CPC classification number: G06F12/0833 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/621

    Abstract: In one embodiment, a computer-implemented method includes detecting a cache miss for a cache line. A resource is reserved on each of one or more remote computing nodes, responsive to the cache miss. A request for a state of the cache line on the one or more remote computing nodes is broadcast to the one or more remote computing nodes, responsive to the cache miss. A resource credit is received from a first remote computing node of the one or more remote computing nodes, responsive to the request. The resource credit indicates that the first remote computing node will not participate in completing the request. The resource on the first remote computing node is released, responsive to receiving the resource credit from the first remote computing node.

    Abstract translation: 在一个实施例中，计算机实现的方法包括检测高速缓存行的高速缓存未命中。 响应于高速缓存未命中，在一个或多个远程计算节点的每一个上保留资源。 响应于高速缓存未命中，向一个或多个远程计算节点广播对一个或多个远程计算节点上的高速缓存行的状态的请求。 响应于该请求，从一个或多个远程计算节点的第一远程计算节点接收资源信用。 资源信用表示第一个远程计算节点不参与完成请求。 响应于从第一远程计算节点接收资源信用，第一远程计算节点上的资源被释放。

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