公开(公告)号：US12158848B2

公开(公告)日：2024-12-03

申请号：US17961598

申请日：2022-10-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sascha Junghans ,  Matthias Klein ,  Julian Heyne ,  Norbert Hagspiel ,  Fahmiyah Samad ,  Ananth Garikapati

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: Combining PCIe partial store commands along cache line boundaries, including: receiving a plurality of Peripheral Component Interface express (PCIe) packets; splitting the plurality of PCIe packets along cache line boundaries to generate a plurality of partial store commands; and combining one or more sets of partial store commands to generate one or more combined partial store commands aligned to the cache line boundaries.