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    ENSURING COMPLETENESS OF INTERFACE SIGNAL CHECKING IN FUNCTIONAL VERIFICATION
    3.
    发明申请
    ENSURING COMPLETENESS OF INTERFACE SIGNAL CHECKING IN FUNCTIONAL VERIFICATION 审中-公开

    公开(公告)号：US20190094299A1

    公开(公告)日：2019-03-28

    申请号：US15714071

    申请日：2017-09-25

    申请人： International Business Machines Corporation

    发明人： Carsten Greiner ,  Minh Cuong Tran ,  Gerrit Koch ,  Joerg Walter

    IPC分类号： G01R31/3183 ,  G06F17/50

    摘要： It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.

    TRACING DATA FROM AN ASYNCHRONOUS INTERFACE
    5.
    发明申请
    TRACING DATA FROM AN ASYNCHRONOUS INTERFACE 有权
    从非同步接口追踪数据

    公开(公告)号：US20150365225A1

    公开(公告)日：2015-12-17

    申请号：US14733249

    申请日：2015-06-08

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC分类号： H04L7/02 ,  H04L7/00

    CPC分类号： G06F11/348 ,  G06F11/3027 ,  G06F11/349 ,  G06F2201/86 ,  H04L7/0045 ,  H04L7/02

    摘要： An apparatus for tracing data from a data bus in a first clock domain operating at a first clock frequency to a trace array in a second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency. The apparatus includes a change detector to detect a change of the data on the data bus in the first clock domain, a trigger responsive to the change detector to send a trigger pulse to the second clock domain, pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch, as well as a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.

    摘要翻译： 一种用于在以第一时钟频率操作的第一时钟域中的数据总线跟踪数据到在第二时钟频率下操作的第二时钟域中的跟踪阵列的装置，其中所述第一时钟频率低于所述第二时钟频率。 该装置包括：变化检测器，用于检测在第一时钟域中的数据总线上的数据的变化;触发响应于变化检测器的触发信号以向第二时钟域发送触发脉冲，响应于第二时钟域的脉冲同步 所述触发脉冲通过元稳定性锁存器将所述触发脉冲与所述第二时钟域的所述第二时钟频率同步，以及响应于所述脉冲同步以从所述数据总线捕获数据的所述第二时钟域中的数据捕获，以及 将捕获的数据存储在跟踪数组中。

    Write and read collision avoidance in single port memory devices
    6.
    发明授权
    Write and read collision avoidance in single port memory devices 有权
    在单端口存储设备中写入和读取冲突避免

    公开(公告)号：US08995210B1

    公开(公告)日：2015-03-31

    申请号：US14090060

    申请日：2013-11-26

    申请人： International Business Machines Corporation

    发明人： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC分类号： G11C7/00 ,  G11C7/22 ,  G11C7/10

    CPC分类号： G11C7/1015 ,  G11C7/1075 ,  G11C2207/2209

    摘要： A method of avoiding a write collision in single port memory devices from two or more independent write operations is described. A first write operation having a first even data object and a first odd data object is received from a first data sender. A second write operation having a second even data object and a second odd data object is received from a second data sender at substantially the same time as the first write operation. The second write operation is delayed so that the first even data object writes to a first single port memory device at a different time than the second even data object writes to the first single port memory device. The second write operation is delayed so that the first odd data object writes to a second single port memory device at a different time than the second odd data object.

    摘要翻译： 描述了避免来自两个或多个独立写入操作的单端口存储器件中的写入冲突的方法。 从第一数据发送器接收具有第一偶数数据对象和第一奇数数据对象的第一写操作。 在与第一写入操作基本相同的时间，从第二数据发送器接收具有第二偶数数据对象和第二奇数数据对象的第二写操作。 第二写操作被延迟，使得第一偶数数据对象以与第二偶数数据对象写入第一单端口存储器设备不同的时间写入第一单端口存储器设备。 第二写操作被延迟，使得第一奇数数据对象在与第二奇数数据对象不同的时间写入第二单端口存储器件。

    Ensuring completeness of interface signal checking in functional verification
    7.
    发明授权
    Ensuring completeness of interface signal checking in functional verification 有权

    公开(公告)号：US10823782B2

    公开(公告)日：2020-11-03

    申请号：US15806922

    申请日：2017-11-08

    申请人： International Business Machines Corporation

    发明人： Carsten Greiner ,  Minh Cuong Tran ,  Gerrit Koch ,  Joerg Walter

    IPC分类号： G01R31/3183 ,  G06F30/33 ,  G06F30/3323 ,  G06F30/30 ,  G06F30/333 ,  G06F30/398

    摘要： It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.

    Initializing I/O devices
    10.
    发明授权
    Initializing I/O devices 有权

    公开(公告)号：US09767048B2

    公开(公告)日：2017-09-19

    申请号：US14862221

    申请日：2015-09-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC分类号： G06F13/10 ,  G06F13/20 ,  G06F13/40

    CPC分类号： G06F13/102 ,  G06F13/20 ,  G06F13/4068

    摘要： A data processing system is provided which includes a processor nest communicatively coupled to an input/output bus by a bus controller, and a service interface controller communicatively coupled to the processor nest. The system includes storage for storing commands for the bus controller and associated command data and resulting status data, the storage being communicatively coupled to the processor nest and the bus controller. The service interface controller is configured, in response to received service commands, to read and write the storage, to execute the command specified in the storage, to retrieve the result of the command, and to store the result in the storage.