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    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY
    5.
    发明申请
    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY 审中-公开

    公开(公告)号：US20170270983A1

    公开(公告)日：2017-09-21

    申请号：US15614072

    申请日：2017-06-05

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Theodore T. Pekny ,  Jae-Kwan Park ,  Viloante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC分类号： G11C7/22 ,  G11C16/26 ,  G11C16/32

    CPC分类号： G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

    摘要： Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

    Overlapping precharge and data write
    6.
    发明授权
    Overlapping precharge and data write 有权

    公开(公告)号：US09685210B1

    公开(公告)日：2017-06-20

    申请号：US15205857

    申请日：2016-07-08

    申请人： QUALCOMM Incorporated

    发明人： Sonia Ghosh ,  Changho Jung

    IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C7/06 ,  G06F12/00

    CPC分类号： G11C7/12 ,  G06F12/00 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1075 ,  G11C11/419 ,  G11C2207/002 ,  G11C2207/2209

    摘要： A memory includes a plurality of memory cells and a plurality of bitlines. Each of the plurality of bitlines is coupled to a corresponding one of the plurality of memory cells. A precharge circuit precharges each of the plurality of bitlines before a read operation and precharges all but one of the plurality of bitlines following the read operation. A write driver drives the one of the plurality of bitlines following the read operation. A method includes precharging each of a plurality of bitlines before a read operation. Each of the plurality of bitlines is coupled to a corresponding one of a plurality of memory cells. The method further includes precharging all but one of the plurality of bitlines following the read operation and driving the one of the plurality of bitlines following the read operation.

    Selectively scheduling memory accesses in parallel based on access speeds of memory
    9.
    发明授权
    Selectively scheduling memory accesses in parallel based on access speeds of memory 有权
    根据存储器的访问速度，并行地选择性地调度存储器访问

    公开(公告)号：US09547444B1

    公开(公告)日：2017-01-17

    申请号：US14311743

    申请日：2014-06-23

    申请人： MARVELL INTERNATIONAL LTD.

    发明人： Xueshi Yang ,  Chi Kong Lee

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/02

    CPC分类号： G06F3/0611 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G11C7/22 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2207/2209

    摘要： Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method includes determining, by a hardware controller, an access speed associated with a page request. The page request is a request to access a memory page in a memory device. The access speed is a number of clock cycles used to access the memory page addressed by the page request. The method also includes scheduling when the page request will be executed based, at least in part, on the access speed by assigning the page request to be executed in parallel with at least one other page request that is to access a different memory page in the memory device using a same number of clock cycles as the page request.

    摘要翻译： 描述了与并行选择性地调度存储器访问相关联的设备，系统，方法和其他实施例。 在一个实施例中，一种方法包括由硬件控制器确定与寻呼请求相关联的访问速度。 页面请求是访问存储设备中的存储器页面的请求。 访问速度是用于访问由页面请求寻址的存储器页面的多个时钟周期。 该方法还包括当至少部分地基于访问速度执行寻呼请求时进行调度，通过将要执行的页面请求与至少一个其他页面请求进行并行执行，该至少一个其他页面请求将访问不同的存储器页面 使用与页面请求相同数量的时钟周期的存储器件。

    Memory cell including transistor and capacitor
    10.
    发明授权
    Memory cell including transistor and capacitor 有权
    存储单元包括晶体管和电容

    公开(公告)号：US09406348B2

    公开(公告)日：2016-08-02

    申请号：US14577491

    申请日：2014-12-19

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Yukio Maehashi

    IPC分类号： G11C5/06 ,  H01L27/11 ,  G11C11/24 ,  G11C7/10

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/1075 ,  G11C8/14 ,  G11C8/16 ,  G11C11/24 ,  G11C2207/2209 ,  H01L27/1116

    摘要： A semiconductor storage device capable of performing low-voltage operation, reducing standby current, and decreasing memory size is provided. The semiconductor storage device is a semiconductor device including first to fourth transistors and a capacitor. The first transistor has a function of supplying a first signal to the capacitor. The capacitor has a function of accumulating electric charge based on the first signal. The second transistor has a function of supplying the electric charge based on the first signal to a gate of the third transistor. The third transistor has a function of outputting a first potential to a wiring and a function of supplying the first potential to a gate of the fourth transistor. The fourth transistor has a function of supplying a second potential to the capacitor through the second transistor.

    摘要翻译： 提供一种能够进行低电压操作，降低待机电流和减小存储器大小的半导体存储装置。 半导体存储装置是包括第一至第四晶体管和电容器的半导体器件。 第一晶体管具有向电容器提供第一信号的功能。 电容器具有基于第一信号累积电荷的功能。 第二晶体管具有基于第一信号将电荷提供给第三晶体管的栅极的功能。 第三晶体管具有向布线输出第一电位的功能和向第四晶体管的栅极提供第一电位的功能。 第四晶体管具有通过第二晶体管向电容器提供第二电位的功能。