公开(公告)号：US10509589B2

公开(公告)日：2019-12-17

申请号：US15329485

申请日：2015-08-13

Applicant: Adesto Technologies Corporation

Inventor： Gideon Intrater ,  Bard Pedersen

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0868

Abstract: A method of controlling a memory device can include: (i) receiving a first read command for a critical byte, where the critical byte resides in a first group of a memory array on the memory device; (ii) reading the critical byte from the memory array in response to the first read command, and providing the critical byte; (iii) reading a next byte in the first group; (iv) outputting the next byte from the first group when a clock pulse; (v) repeating the reading the next byte and the outputting the next byte for each byte in the first group; (vi) reading a first byte in a second group of the memory array, where the second group is sequential to the first group, and where each group is allocated to a cache line; and (vii) outputting the first byte from the second group when a clock pulse is received.

公开(公告)号：US10031869B1

公开(公告)日：2018-07-24

申请号：US14665831

申请日：2015-03-23

Applicant: Adesto Technologies Corporation

Inventor： Gideon Intrater ,  Bard Pedersen ,  Paul Hill

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/16 ,  G06F12/122 ,  G11C11/406 ,  G11C7/10 ,  G06F12/0831 ,  G06F12/0802 ,  G06F12/0868

Abstract: In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.

公开(公告)号：US20210157389A1

公开(公告)日：2021-05-27

申请号：US17034154

申请日：2020-09-28

Applicant: Adesto Technologies Corporation

Inventor： Gideon Intrater

IPC: G06F1/3234 ,  G06F1/3225 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/409 ,  G11C5/14 ,  G11C8/18

Abstract: A method of controlling a memory device can include: determining, by the memory device, a time duration in which the memory device is in a standby mode; automatically switching the memory device from the standby mode to a power down mode in response to the time duration exceeding a predetermined duration; exiting from the power down mode in response to signaling from a host device via an interface; and toggling a data strobe when data is ready to be output from the memory device in response to a read command from the host device.

公开(公告)号：US20180166130A1

公开(公告)日：2018-06-14

申请号：US15568713

申请日：2016-05-02

Applicant: Adesto Technologies Corporation

Inventor： Gideon Intrater ,  Bard Pedersen ,  Shane Hollmer ,  Derric Lewis ,  Stephen Trinh

IPC: G11C11/419 ,  G11C13/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/02 ,  G11C7/22 ,  G11C8/12

CPC classification number: G11C11/419 ,  G11C5/141 ,  G11C7/22 ,  G11C8/12 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2209 ,  G11C2211/5623 ,  G11C2216/22

Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.

公开(公告)号：US20170256297A1

公开(公告)日：2017-09-07

申请号：US15061732

申请日：2016-03-04

Applicant: Adesto Technologies Corporation

Inventor： Gideon Intrater ,  Bard Pedersen ,  Ishai Naveh

IPC: G11C8/06 ,  G11C7/22 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C8/06 ,  G11C5/066 ,  G11C7/062 ,  G11C7/103 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/22 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/5006

Abstract: A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.

公开(公告)号：US11681352B2

公开(公告)日：2023-06-20

申请号：US17034154

申请日：2020-09-28

Applicant: Adesto Technologies Corporation

Inventor： Gideon Intrater

IPC: G06F1/3234 ,  G06F1/3225 ,  G11C11/4074 ,  G11C8/18 ,  G11C11/409 ,  G11C5/14 ,  G11C11/4076 ,  G06F13/00 ,  G06F1/3206 ,  G06F1/3203 ,  G06F3/06

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/148 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4074 ,  G11C11/4076 ,  G06F1/3203 ,  G06F1/3206 ,  G06F3/0679 ,  G06F13/00

Abstract: A method of controlling a memory device can include: determining, by the memory device, a time duration in which the memory device is in a standby mode; automatically switching the memory device from the standby mode to a power down mode in response to the time duration exceeding a predetermined duration; exiting from the power down mode in response to signaling from a host device via an interface; and toggling a data strobe when data is ready to be output from the memory device in response to a read command from the host device.

公开(公告)号：US20220092004A1

公开(公告)日：2022-03-24

申请号：US17030594

申请日：2020-09-24

Applicant: Adesto Technologies Corporation

Inventor： Gideon Intrater ,  Bard Pedersen

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/02 ,  G06F13/42

Abstract: A method of controlling a read request can include: receiving, in a host device, the read request from a bus master, where the host device is coupled to a memory device by an interface; determining a configuration state of the read request; comparing an attribute of the read request against a predetermined attribute stored in the host device; adjusting the configuration state of the read request when the attribute of the read request matches the predetermined attribute; and sending the read request with the adjusted configuration state from the host device to the memory device via the interface.

公开(公告)号：US10409505B2

公开(公告)日：2019-09-10

申请号：US15576941

申请日：2016-04-13

Applicant: Adesto Technologies Corporation

Inventor： Derric Lewis ,  John Dinh ,  Gideon Intrater ,  Nathan Gonzales

IPC: G06F3/06 ,  G06F1/24 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/42 ,  G11C5/14 ,  G11C11/417

Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

公开(公告)号：US20180025761A1

公开(公告)日：2018-01-25

申请号：US15720244

申请日：2017-09-29

Applicant: Adesto Technologies Corporation

Inventor： Gideon Intrater ,  Bard Pedersen ,  Ishai Naveh

IPC: G11C8/06 ,  G11C7/10 ,  G11C7/22 ,  G11C7/06

CPC classification number: G11C8/06 ,  G11C5/066 ,  G11C7/062 ,  G11C7/103 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/22 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/5006

Abstract: A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.

公开(公告)号：US10275372B1

公开(公告)日：2019-04-30

申请号：US16010960

申请日：2018-06-18

Applicant: Adesto Technologies Corporation

Inventor： Gideon Intrater ,  Bard Pedersen ,  Paul Hill

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/16 ,  G11C7/10 ,  G11C11/406 ,  G06F12/0831 ,  G06F12/122 ,  G06F12/0868 ,  G06F12/0802

Abstract: In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.