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    Static random access memories with programmable impedance elements and methods and devices including the same
    1.
    发明授权
    Static random access memories with programmable impedance elements and methods and devices including the same 有权

    公开(公告)号：US10777268B2

    公开(公告)日：2020-09-15

    申请号：US16188224

    申请日：2018-11-12

    Applicant: Adesto Technologies Corporation

    Inventor： Venkatesh P. Gopinath ,  Nathan Gonzales

    IPC: G11C13/00 ,  G11C11/412 ,  G11C14/00

    Abstract: An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices. The first resistive element can be conductively connected to a first data latching node by a first vertical connection. The second resistive element can be conductively connected to a second data latching node by a second vertical connection. Each resistive element can include at least one memory layer that is capable of being programmed between at least a high and lower resistance state by application of electric fields, the resistive elements having only the high resistance state.

    Write parameter switching in a memory device
    3.
    发明授权
    Write parameter switching in a memory device 有权

    公开(公告)号：US10191666B1

    公开(公告)日：2019-01-29

    申请号：US14875464

    申请日：2015-10-05

    Applicant: Adesto Technologies Corporation

    Inventor： Derric Jawaher Herman Lewis ,  John Dinh ,  Nathan Gonzales

    IPC: G06F3/06

    Abstract: A method of controlling write parameter selection in a memory device, can include: (i) storing a configuration set number in a configuration register, where the configuration register is accessible by a user via an interface; (ii) receiving a write command from a host via the interface; (iii) comparing the stored configuration set number against set numbers in a register block to determine a match or a mismatch; (iv) downloading configuration bits from a memory array into the register block in response to the mismatch determination; (v) selecting a configuration set corresponding to the stored configuration set number from the register block in response to the match determination; and (vi) using the selected configuration set to perform a write operation on the memory device to execute the write command.

    Memory device ultra-deep power-down mode exit control
    6.
    发明授权
    Memory device ultra-deep power-down mode exit control 有权

    公开(公告)号：US09922684B2

    公开(公告)日：2018-03-20

    申请号：US15409270

    申请日：2017-01-18

    Applicant: Adesto Technologies Corporation

    Inventor： Bard M. Pedersen ,  Derric Lewis ,  John Dinh ,  Gideon Intrater ,  Nathan Gonzales

    IPC: G11C5/14 ,  G11C11/4074

    CPC classification number: G11C5/148 ,  G11C5/14 ,  G11C5/147 ,  G11C11/4074

    Abstract: A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.

    MEMORY DEVICE ULTRA-DEEP POWER-DOWN MODE EXIT CONTROL
    7.
    发明申请
    MEMORY DEVICE ULTRA-DEEP POWER-DOWN MODE EXIT CONTROL 有权

    公开(公告)号：US20170236561A1

    公开(公告)日：2017-08-17

    申请号：US15409270

    申请日：2017-01-18

    Applicant: Adesto Technologies Corporation

    Inventor： Bard M. Pedersen ,  Derric Lewis ,  John Dinh ,  Gideon Intrater ,  Nathan Gonzales

    IPC: G11C5/14

    CPC classification number: G11C5/148 ,  G11C5/14 ,  G11C5/147 ,  G11C11/4074

    Abstract: A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.

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