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    MEMORY DEVICES AND METHODS HAVING ADAPTABLE READ THRESHOLD LEVELS
    3.
    发明申请
    MEMORY DEVICES AND METHODS HAVING ADAPTABLE READ THRESHOLD LEVELS 有权
    具有适应性读取阈值水平的存储器件和方法

    公开(公告)号：US20130258753A1

    公开(公告)日：2013-10-03

    申请号：US13851011

    申请日：2013-03-26

    申请人： ADESTO TECHNOLOGIES CORPORATION

    发明人： Venkatesh P. Gopinath ,  Foroozan Sarah Koushan ,  Derric Jawaher Herman Lewis

    IPC分类号： G11C13/00

    CPC分类号： G11C13/004 ,  G11C11/5614 ,  G11C13/0011 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/28

    摘要： A method can include determining at least one use characteristic for the memory cells comprising a solid electrolyte, the use characteristic corresponding to a number of times the memory cells have been programmed to at least one impedance level; and adjusting a read threshold level for the memory cells based on at least the use characteristic, the read threshold level determining data values stored in the memory cells in a read operation.

    摘要翻译： 一种方法可以包括确定包括固体电解质的存储单元的至少一个使用特性，所述使用特性对应于存储器单元已被编程至少一个阻抗水平的次数; 以及至少基于所述使用特性来调整所述存储器单元的读取阈值电平，所述读取阈值电平确定在读取操作中存储在所述存储器单元中的数据值。

    Reference circuits and methods for resistive memories
    4.
    发明授权
    Reference circuits and methods for resistive memories 有权

    公开(公告)号：US10984861B1

    公开(公告)日：2021-04-20

    申请号：US16032012

    申请日：2018-07-10

    申请人： Adesto Technologies Corporation

    发明人： Ishai Naveh ,  Venkatesh P. Gopinath ,  John Dinh ,  Mark T. Ramsbey

    IPC分类号： G11C13/00

    摘要： A memory device can include a plurality of memory cells formed in a substrate, each having a resistive element programmable between at least two different resistance states, including memory cells configured to store data received by the memory device, and reference cells; a reference circuit formed in the substrate configured to generate at least a first reference resistance from resistances of a plurality of reference cells; a sense circuit formed in the substrate coupled to the memory cells and at least the first reference resistance and configured to compare a resistance of a selected memory cell to at least the first reference resistance to determine the data stored by the selected memory cell.

    Static random access memories with programmable impedance elements and methods and devices including the same
    5.
    发明授权
    Static random access memories with programmable impedance elements and methods and devices including the same 有权

    公开(公告)号：US10777268B2

    公开(公告)日：2020-09-15

    申请号：US16188224

    申请日：2018-11-12

    申请人： Adesto Technologies Corporation

    发明人： Venkatesh P. Gopinath ,  Nathan Gonzales

    IPC分类号： G11C13/00 ,  G11C11/412 ,  G11C14/00

    摘要： An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices. The first resistive element can be conductively connected to a first data latching node by a first vertical connection. The second resistive element can be conductively connected to a second data latching node by a second vertical connection. Each resistive element can include at least one memory layer that is capable of being programmed between at least a high and lower resistance state by application of electric fields, the resistive elements having only the high resistance state.

    Programmable impedance memory device and related methods
    6.
    发明授权
    Programmable impedance memory device and related methods 有权

    公开(公告)号：US10181496B1

    公开(公告)日：2019-01-15

    申请号：US15143310

    申请日：2016-04-29

    申请人： Adesto Technologies Corporation

    发明人： Ming Sang Kwan ,  Venkatesh P. Gopinath

    IPC分类号： H01L29/786 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00

    摘要： A memory device can include at least one plate structure formed over a semiconductor substrate; an active region formed within the semiconductor substrate without lateral isolation structures; a plurality of bit line contact groups, each including bit line contacts to the active region disposed in a first direction; a plurality of storage contact groups, each including storage contacts to the active region disposed in the first direction; a plurality of gate structures, each including a main section extending in the first direction, and disposed between one bit line contact group and an adjacent storage contact group; and a two-terminal storage element disposed between each bit line contact and the at least one plate structure.

    Resistive switching memory with cell access by analog signal controlled transmission gate
    10.
    发明授权
    Resistive switching memory with cell access by analog signal controlled transmission gate 有权
    电阻式开关存储器，具有模拟信号控制传输门的单元访问

    公开(公告)号：US09472272B2

    公开(公告)日：2016-10-18

    申请号：US14628280

    申请日：2015-02-22

    申请人： Adesto Technologies Corporation

    发明人： Venkatesh P. Gopinath ,  Deepak Kamalanathan ,  Daniel Wang

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0011 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/74 ,  G11C2213/79

    摘要： In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.

    摘要翻译： 在一个实施例中，半导体存储器件包括多个电阻式开关存储器单元，其中每个电阻式开关存储器单元可以包括：（i）具有阳极和阴极的可编程阻抗元件; （ii）被配置为控制对所述可编程阻抗元件的访问的字线对，其中所述字线对包括第一和第二字线; （iii）具有耦合到阴极的源极，耦合到位线的漏极和耦合到第一字线的栅极的PMOS晶体管; 以及（iv）具有耦合到所述位线的源极，耦合到所述阴极的漏极和耦合到所述第二字线的栅极的NMOS晶体管。