公开(公告)号：US20180205012A1

公开(公告)日：2018-07-19

申请号：US15746420

申请日：2016-07-20

Applicant: Adesto Technologies Corporation

Inventor： Mark T. Ramsbey ,  Venkatesh P. Gopinath ,  Jeffrey Allan Shields ,  Kuei Chang Tsai ,  Chakravarthy Gopalan ,  Michael A. Van Buskirk

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528 ,  H01L23/522 ,  G11C13/00

CPC classification number: H01L45/085 ,  G11C13/0011 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/79 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253

Abstract: An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.

公开(公告)号：US09412945B1

公开(公告)日：2016-08-09

申请号：US13830315

申请日：2013-03-14

Applicant: Adesto Technologies Corporation

Inventor： Kuei Chang Tsai ,  Jeffrey Allan Shields ,  Pascal Verrier

IPC: H01L29/02 ,  H01L45/00

CPC classification number: H01L45/1683 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

Abstract: A storage element can include a bottom structure having at least one edge formed by a top surface and a side surface; a programmable layer, programmable between at least two different impedance states, and formed over the at least one edge and in contact with a portion of the bottom structure; an insulating layer that extends above the top surface of the bottom structure having an opening to the bottom structure formed therein, the opening having sloped sides; and at least one top layer formed within the opening and in contact with the programmable layer. Methods of making such a storage element are also disclosed.

Abstract translation: 存储元件可以包括底部结构，其具有由顶表面和侧表面形成的至少一个边缘; 可编程层，其可在至少两个不同阻抗状态之间编程，并且形成在所述至少一个边缘上并与所述底部结构的一部分接触; 绝缘层，其在底部结构的顶表面上方延伸，具有形成在其中的底部结构的开口，该开口具有倾斜的侧面; 以及形成在开口内并与可编程层接触的至少一个顶层。 还公开了制造这种存储元件的方法。

公开(公告)号：US11056646B2

公开(公告)日：2021-07-06

申请号：US15746420

申请日：2016-07-20

Applicant: Adesto Technologies Corporation

Inventor： Mark T. Ramsbey ,  Venkatesh P. Gopinath ,  Jeffrey Allan Shields ,  Kuei Chang Tsai ,  Chakravarthy Gopalan ,  Michael A. Van Buskirk

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.

公开(公告)号：US09595671B1

公开(公告)日：2017-03-14

申请号：US15214224

申请日：2016-07-19

Applicant: Adesto Technologies Corporation

Inventor： Kuei Chang Tsai ,  Jeffrey Allan Shields ,  Pascal Verrier

IPC: H01L21/20 ,  H01L45/00

CPC classification number: H01L45/1683 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

Abstract: A method can include forming a bottom structure with a top surface and a side surface that form at least one edge; forming an opening with sloped sides through at least one insulating layer to expose at least a portion of the top surface of the bottom structure; forming a programmable layer over the at least one edge, in contact with the sloped sides of the opening and the top surface of the bottom structure; and forming a top layer over the programmable layer and opening; wherein the programmable layer is programmable between at least two different impedance states.

Abstract translation: 方法可以包括形成具有顶表面和形成至少一个边缘的侧表面的底部结构; 通过至少一个绝缘层形成具有倾斜侧面的开口以暴露底部结构的顶表面的至少一部分; 在所述至少一个边缘上形成与所述开口的倾斜侧面和所述底部结构的顶表面接触的可编程层; 并在可编程层上形成顶层并打开; 其中所述可编程层可在至少两个不同阻抗状态之间编程。

公开(公告)号：US20140293676A1

公开(公告)日：2014-10-02

申请号：US14195787

申请日：2014-03-03

Applicant: ADESTO TECHNOLOGIES CORPORATION

Inventor： Wei Ti Lee ,  Janet Wang ,  Chakravarthy Gopalan ,  Jeffrey Allan Shields ,  Yi Ma ,  Kuei Chang Tsai ,  John Sanchez ,  John Ross Jameson ,  Michael Van Buskirk ,  Venkatesh P. Gopinath

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16

Abstract: A memory element programmable between different impedance states can include a first electrode; a switching layer formed in contact with the first electrode and including at least one metal oxide; and a buffer layer in contact with the switching layer. A buffer layer can include a first metal, tellurium, a third element, and a second metal distributed within the buffer layer. A second electrode can be in contact with the buffer layer.

Abstract translation: 可编程在不同阻抗状态之间的存储元件可包括第一电极; 开关层，与所述第一电极接触并且包括至少一种金属氧化物; 以及与开关层接触的缓冲层。 缓冲层可以包括分布在缓冲层内的第一金属，碲，第三元素和第二金属。 第二电极可以与缓冲层接触。