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1.发明申请PROGRAMMABLE RESISTANCE MEMORY ELEMENTS WITH ELECTRODE INTERFACE LAYER AND MEMORY DEVICES INCLUDING THE SAME 审中-公开具有电极接口层的可编程电阻存储器元件和包括其的存储器件公开(公告)号：US20160043310A1
公开(公告)日：2016-02-11
申请号：US14791412
申请日：2015-07-04
发明人： Chakravarthy Gopalan , Wei Ti Lee , Yi Ma , Jeffrey Allan Shields
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/16 , H01L45/1608 , H01L45/1625
摘要： A memory element can include a first electrode comprising at least a first element; a second electrode formed of a conductive material; and a memory layer comprising a memory material programmable between different resistance states. The first element can be ion conductible within the memory material. A second electrode can include an interface layer in contact with the memory layer. The interface layer being formed by inclusion of at least one modifier element not present in a remainder of the second electrode and not ion conductible within the memory material.
摘要翻译： 存储元件可以包括包括至少第一元件的第一电极; 由导电材料形成的第二电极; 以及包括可在不同电阻状态之间编程的存储器材料的存储器层。 第一个元素可以在记忆材料内离子传导。 第二电极可以包括与存储层接触的界面层。 界面层通过包含不存在于第二电极的其余部分中的至少一种改性剂元件形成，并且不在记忆材料内导电。
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2.发明授权Solid electrolyte memory elements with electrode interface for improved performance 有权具有电极接口的固体电解质存储元件，以提高性能公开(公告)号：US09099633B2
公开(公告)日：2015-08-04
申请号：US13850267
申请日：2013-03-25
发明人： Chakravarthy Gopalan , Wei Ti Lee , Yi Ma , Jeffrey Allan Shields
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/16 , H01L45/1608 , H01L45/1625
摘要： A memory element can include a first electrode; a second electrode; and a memory material programmable between different resistance states, the memory material disposed between the first electrode and the second electrode and comprising a solid electrolyte with at least one modifier element formed therein; wherein the first electrode is an anode electrode that includes an anode element that is ion conductible in the solid electrolyte, the anode element being different than the modifier element.
摘要翻译： 存储元件可以包括第一电极; 第二电极; 以及存储材料，其可编程在不同的电阻状态之间，所述存储材料设置在所述第一电极和所述第二电极之间，并且包括具有形成在其中的至少一个改性元件的固体电解质 其中所述第一电极是包括在所述固体电解质中可离子传导的阳极元件的阳极电极，所述阳极元件不同于所述改性剂元件。
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3.发明申请公开(公告)号：US20180205012A1
公开(公告)日：2018-07-19
申请号：US15746420
申请日：2016-07-20
发明人： Mark T. Ramsbey , Venkatesh P. Gopinath , Jeffrey Allan Shields , Kuei Chang Tsai , Chakravarthy Gopalan , Michael A. Van Buskirk
IPC分类号： H01L45/00 , H01L27/24 , H01L23/528 , H01L23/522 , G11C13/00
CPC分类号： H01L45/085 , G11C13/0011 , G11C13/0028 , G11C2213/71 , G11C2213/79 , H01L23/5226 , H01L23/528 , H01L27/2436 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/1253
摘要： An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.
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4.发明授权Storage elements, structures and methods having edgeless features for programmable layer(s) 有权具有可编程层的无边缘特征的存储元件，结构和方法公开(公告)号：US09412945B1
公开(公告)日：2016-08-09
申请号：US13830315
申请日：2013-03-14
CPC分类号： H01L45/1683 , H01L45/085 , H01L45/1233 , H01L45/124 , H01L45/1246 , H01L45/1266 , H01L45/141 , H01L45/146 , H01L45/16
摘要： A storage element can include a bottom structure having at least one edge formed by a top surface and a side surface; a programmable layer, programmable between at least two different impedance states, and formed over the at least one edge and in contact with a portion of the bottom structure; an insulating layer that extends above the top surface of the bottom structure having an opening to the bottom structure formed therein, the opening having sloped sides; and at least one top layer formed within the opening and in contact with the programmable layer. Methods of making such a storage element are also disclosed.
摘要翻译： 存储元件可以包括底部结构，其具有由顶表面和侧表面形成的至少一个边缘; 可编程层，其可在至少两个不同阻抗状态之间编程，并且形成在所述至少一个边缘上并与所述底部结构的一部分接触; 绝缘层，其在底部结构的顶表面上方延伸，具有形成在其中的底部结构的开口，该开口具有倾斜的侧面; 以及形成在开口内并与可编程层接触的至少一个顶层。 还公开了制造这种存储元件的方法。
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5.发明申请SOLID ELECTROLYTE MEMORY ELEMENTS WITH ELECTRODE INTERFACE FOR IMPROVED PERFORMANCE 有权具有电极接口的固体电解质存储元件，用于改进性能公开(公告)号：US20130285004A1
公开(公告)日：2013-10-31
申请号：US13850267
申请日：2013-03-25
发明人： Chakravarthy Gopalan , Wei Ti Lee , Yi Ma , Jeffrey Allan Shields
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/16 , H01L45/1608 , H01L45/1625
摘要： A memory element can include a first electrode; a second electrode; and a memory material programmable between different resistance states, the memory material disposed between the first electrode and the second electrode and comprising a solid electrolyte with at least one modifier element formed therein; wherein the first electrode is an anode electrode that includes an anode element that is ion conductible in the solid electrolyte, the anode element being different than the modifier element.
摘要翻译： 存储元件可以包括第一电极; 第二电极; 以及存储材料，其可编程在不同的电阻状态之间，所述存储材料设置在所述第一电极和所述第二电极之间，并且包括具有形成在其中的至少一个改性元件的固体电解质 其中所述第一电极是包括在所述固体电解质中可离子传导的阳极元件的阳极电极，所述阳极元件不同于所述改性剂元件。
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6.发明授权公开(公告)号：US11056646B2
公开(公告)日：2021-07-06
申请号：US15746420
申请日：2016-07-20
发明人： Mark T. Ramsbey , Venkatesh P. Gopinath , Jeffrey Allan Shields , Kuei Chang Tsai , Chakravarthy Gopalan , Michael A. Van Buskirk
IPC分类号： H01L45/00 , G11C13/00 , H01L27/24 , H01L23/522 , H01L23/528
摘要： An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.
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7.发明授权Methods of fabricating storage elements and structures having edgeless features for programmable layer(s) 有权制造具有可编程层的无边缘特征的存储元件和结构的方法公开(公告)号：US09595671B1
公开(公告)日：2017-03-14
申请号：US15214224
申请日：2016-07-19
CPC分类号： H01L45/1683 , H01L45/085 , H01L45/1233 , H01L45/124 , H01L45/1246 , H01L45/1266 , H01L45/141 , H01L45/146 , H01L45/16
摘要： A method can include forming a bottom structure with a top surface and a side surface that form at least one edge; forming an opening with sloped sides through at least one insulating layer to expose at least a portion of the top surface of the bottom structure; forming a programmable layer over the at least one edge, in contact with the sloped sides of the opening and the top surface of the bottom structure; and forming a top layer over the programmable layer and opening; wherein the programmable layer is programmable between at least two different impedance states.
摘要翻译： 方法可以包括形成具有顶表面和形成至少一个边缘的侧表面的底部结构; 通过至少一个绝缘层形成具有倾斜侧面的开口以暴露底部结构的顶表面的至少一部分; 在所述至少一个边缘上形成与所述开口的倾斜侧面和所述底部结构的顶表面接触的可编程层; 并在可编程层上形成顶层并打开; 其中所述可编程层可在至少两个不同阻抗状态之间编程。
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公开(公告)号：US20140293676A1
公开(公告)日：2014-10-02
申请号：US14195787
申请日：2014-03-03
发明人： Wei Ti Lee , Janet Wang , Chakravarthy Gopalan , Jeffrey Allan Shields , Yi Ma , Kuei Chang Tsai , John Sanchez , John Ross Jameson , Michael Van Buskirk , Venkatesh P. Gopinath
CPC分类号： H01L45/08 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16
摘要： A memory element programmable between different impedance states can include a first electrode; a switching layer formed in contact with the first electrode and including at least one metal oxide; and a buffer layer in contact with the switching layer. A buffer layer can include a first metal, tellurium, a third element, and a second metal distributed within the buffer layer. A second electrode can be in contact with the buffer layer.
摘要翻译： 可编程在不同阻抗状态之间的存储元件可包括第一电极; 开关层，与所述第一电极接触并且包括至少一种金属氧化物; 以及与开关层接触的缓冲层。 缓冲层可以包括分布在缓冲层内的第一金属，碲，第三元素和第二金属。 第二电极可以与缓冲层接触。
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公开(公告)号：US20170279045A1
公开(公告)日：2017-09-28
申请号：US15480673
申请日：2017-04-06
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , G11C13/0011 , G11C2213/50 , H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1266 , H01L45/16 , H01L45/1608
摘要： A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at least one switching layer is programmable between different impedance states by application of electric fields via that first and second electrode. Methods of forming such memory elements are also disclosed.
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10.发明授权Memory cells with vertically integrated tunnel access device and programmable impedance element 有权具有垂直集成隧道访问设备和可编程阻抗元件的存储单元公开(公告)号：US09391270B1
公开(公告)日：2016-07-12
申请号：US14530460
申请日：2014-10-31
发明人： Venkatesh P. Gopinath , Jeffrey Allan Shields , Yi Ma , Chakravarthy Gopalan , Ming Kwon , John Dinh
CPC分类号： H01L45/08 , H01L27/2418 , H01L27/2436
摘要： A memory device can include a plurality of memory cells formed over a substrate, each memory cell including a tunnel access device that enables current flow in at least one direction predominantly due to tunneling, and a storage element programmable between different impedance states by a reduction-oxidation reaction within at least one memory layer formed between two electrodes; wherein the tunneling access device and programmable impedance element are vertically stacked over one another.
摘要翻译： 存储器件可以包括形成在衬底上的多个存储器单元，每个存储器单元包括隧道访问器件，其能够主要由于隧道而在至少一个方向上流动电流，并且存储元件可通过减少 - 在两个电极之间形成的至少一个存储层内的氧化反应; 其中所述隧道访问装置和可编程阻抗元件彼此垂直地堆叠。
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