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公开(公告)号：US12222791B2
公开(公告)日：2025-02-11
申请号：US17112933
申请日：2020-12-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ramdas P. Kachare , Wentao Wu , Sompong Paul Olarig
IPC: G06F1/3234 , G06F1/3221 , G06F1/3225 , G06F1/3287 , G06F11/30 , G06F11/34 , G06F1/26 , G06F1/28 , G06F1/30 , G06F11/20
Abstract: A storage system comprises one or more storage devices, power supplies supplying power to the storage device, a processor that performs in response to determining that the total power consumption of the one or more storage devices is less than a first percentage threshold of a load of the active power supplies, deactivating one or more of the active power supplies until the total power consumption is equal to or greater than the first percentage threshold of a load of each of the active power supplies, and in response to determining that the total power consumption is equal to or greater than a second percentage threshold of a load of each of the active power supplies, activating one or more of the deactivated ones of the power supplies until the total power consumption is less than the second percentage threshold of the load of each of the active power supplies.
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公开(公告)号：US12222788B2
公开(公告)日：2025-02-11
申请号：US17918583
申请日：2020-06-08
Applicant: Mitsubishi Electric Corporation
Inventor： Ryota Kitagawa , Katsuhisa Ogasawara
IPC: G06F1/3203 , G06F1/3225 , G06F1/3228 , G06F1/3234 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/50
Abstract: An information processing system includes an execution block computational strength data area, a roofline model data storage unit, a computational strength data acquisition unit, and a performance power control unit. The execution block computational strength data area holds computational strength data of each execution block constituting an arithmetic application that operates in a computer system including a processor and a main storage apparatus. The roofline model data storage unit holds a roofline model corresponding to an operation frequency and the number of cores of the processor, and an operation frequency of the main storage apparatus. The computational strength data acquisition unit acquires computational strength data of each execution block. The performance power control unit controls an operation frequency and the number of cores of the processor and an operation frequency of the main storage apparatus based on the roofline model and the computational strength data of each execution block.
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公开(公告)号：US12189451B2
公开(公告)日：2025-01-07
申请号：US18323945
申请日：2023-05-25
Applicant: Western Digital Technologies, Inc.
Inventor： Dmitry Vaysman , Eran Erez , Judah Gamliel Hahn , Sartaj Ajrawat
IPC: G06F1/32 , G06F1/3225 , G06F1/3234
Abstract: The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.
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公开(公告)号：US20250004524A1
公开(公告)日：2025-01-02
申请号：US18712222
申请日：2022-11-22
Inventor： Yaoyu HUA , Ruijie WANG , Xuetao CUI , Lupan WANG
IPC: G06F1/30 , G06F1/26 , G06F1/3225
Abstract: Provided are a power supply method and device for a storage array, and a server. The method includes: acquiring state data for representing power supply state of power modules first; determining, according to the state data, whether the storage array reaches a power failure triggering condition; and when the storage array reaches the power failure triggering condition, controlling the current power module to be switched to other power modules or standby batteries.
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公开(公告)号：US12181949B2
公开(公告)日：2024-12-31
申请号：US17575647
申请日：2022-01-14
Applicant: Tsang-Ming Chang , Yi-Hsun Lin , Ching-Ji Liang , Hsun-Hung Wang , Hao-Jung Chiou
Inventor： Tsang-Ming Chang , Yi-Hsun Lin , Ching-Ji Liang , Hsun-Hung Wang , Hao-Jung Chiou
IPC: G06F1/32 , G06F1/3212 , G06F1/3225 , G06F1/3287
Abstract: A power management device and a management method thereof are provided. The power management device includes a switch, a detection circuit and a controller. The switch receives an external power. The detection circuit receives an internal power and at least one operation power. The detection circuit determines whether at least one of the internal power and the operation power is in a preset specification range or not to generate a protection activate signal. The controller sets a protection flag according to the protection activate signal, and generates a control signal according to the protection flag by executing an application program. The controller transmits the control signal to turn off the switch.
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公开(公告)号：US20240427698A1
公开(公告)日：2024-12-26
申请号：US18829548
申请日：2024-09-10
Applicant: Micron Technology, Inc.
Inventor： Steven R. NARUM , Huapeng GUAN
IPC: G06F12/02 , G06F1/3225
Abstract: A memory device may detect a memory operation that updates a level two volatile (L2V) entry stored in an L2V table. Each L2V entry in the L2V table may indicate a mapping between a respective logical block address (LBA) and a respective user data physical address in non-volatile memory. The memory operation may cause a mapping between an LBA indicated in the L2V entry and a user data physical address indicated in the L2V entry to become invalid. The memory device may store, in a volatile memory log, an indication of an LBA region that includes the LBA. The memory device may detect that an L2 transfer condition, associated with the volatile memory log, is satisfied. The memory device may copy, from volatile memory to non-volatile memory, every L2V entry that indicates an LBA included in the LBA region based on detecting that the L2 transfer condition is satisfied.
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公开(公告)号：US20240402900A1
公开(公告)日：2024-12-05
申请号：US18802520
申请日：2024-08-13
Applicant: QUALCOMM Incorporated
IPC: G06F3/0485 , G06F1/3225 , G06F1/3228 , G06F1/3234 , G06F1/3287 , G06F3/0481 , G06F3/0482 , G06F3/0483 , G06F3/04842 , G06F9/4401 , G09G5/14 , H04M1/72403 , H04W52/02
Abstract: In an electronic device capable of running multiple software applications concurrently, applications, documents, cards, or other activities can be selected for hibernation so as to free up system resources for other activities that are in active use. A determination is made as to which activities should hibernate, for example based on a determination as to which activities have not been used recently or based on relative resource usage. When an activity is to hibernate, its state is preserved on a storage medium such as a disk, so that the activity can later be revived in the same state and the user can continue with the same task that was being performed before the activity entered hibernation.
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公开(公告)号：US12112033B2
公开(公告)日：2024-10-08
申请号：US17938293
申请日：2022-10-05
Applicant: QUALCOMM Incorporated
IPC: G06F1/32 , G06F1/3225 , G06F1/3234 , G06F3/0481 , G06F3/0482 , G06F3/0483 , G06F3/04842 , G06F3/0485 , G06F9/4401 , G09G5/14 , G06F1/3228 , G06F1/3287 , H04M1/72403 , H04W52/02
CPC classification number: G06F3/0485 , G06F1/3225 , G06F1/3243 , G06F1/3275 , G06F3/0481 , G06F3/0482 , G06F3/0483 , G06F3/04842 , G06F9/4418 , G09G5/14 , G06F1/3228 , G06F1/3287 , H04M1/72403 , H04W52/0264 , Y02D10/00 , Y02D30/50 , Y02D30/70
Abstract: In an electronic device capable of running multiple software applications concurrently, applications, documents, cards, or other activities can be selected for hibernation so as to free up system resources for other activities that are in active use. A determination is made as to which activities should hibernate, for example based on a determination as to which activities have not been used recently or based on relative resource usage. When an activity is to hibernate, its state is preserved on a storage medium such as a disk, so that the activity can later be revived in the same state and the user can continue with the same task that was being performed before the activity entered hibernation.
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公开(公告)号：US12105574B2
公开(公告)日：2024-10-01
申请号：US17729854
申请日：2022-04-26
Applicant: Western Digital Technologies, Inc.
Inventor： Refael Ben-Rubi
IPC: G06F1/3234 , G06F1/08 , G06F1/3203 , G06F1/3221 , G06F1/3225 , G06F1/324 , G06F3/06 , G06F9/54 , G06F11/34
CPC classification number: G06F1/3268 , G06F1/324 , G06F1/08 , G06F1/3203 , G06F1/3221 , G06F1/3225 , G06F1/3275 , G06F3/0625 , G06F3/0656 , G06F9/546 , G06F11/3409
Abstract: The present disclosure generally relates to ensuring a data storage device consumes as little power as possible. Different HW modules in the data storage device can operate at different frequencies to ensure any bottleneck HW modules operate at as fast a frequency as possible, while non-bottleneck HW modules operate at slower frequencies and hence, consume less power. The frequency for each HW modules is dynamic and is adjusted based upon detected bottlenecks so that the data storage device can operate as efficiently as possible and consume as little power as possible.
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公开(公告)号：US12099379B2
公开(公告)日：2024-09-24
申请号：US18079324
申请日：2022-12-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anand Kumar G
IPC: G06F1/00 , G06F1/14 , G06F1/3225 , G06F1/3237 , G06F1/3203 , G06F1/3287
CPC classification number: G06F1/14 , G06F1/3225 , G06F1/3237 , G06F1/3203 , G06F1/3287
Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.
