公开(公告)号：US20180033495A1

公开(公告)日：2018-02-01

申请号：US15225744

申请日：2016-08-01

Applicant: QUALCOMM Incorporated

Inventor： Sonia Ghosh ,  Changho Jung

IPC: G11C29/00 ,  G11C7/22 ,  G11C7/06

CPC classification number: G11C29/781 ,  G11C7/065 ,  G11C7/22 ,  G11C29/702 ,  G11C29/832 ,  G11C29/846 ,  G11C29/848

Abstract: A memory includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to select for their corresponding column or an immediately-subsequent column to their corresponding column.

公开(公告)号：US11251123B1

公开(公告)日：2022-02-15

申请号：US17002486

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Sunil Sharma ,  Rahul Biradar ,  Sonia Ghosh

IPC: H01L23/528 ,  H01L27/11 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/522

Abstract: Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exemplary aspects, the SRAM bit cell employs an increased width write word line based on a circuit cell layout area savings achieved by employing a reduced width read word line. Increasing the width of the write word line can reduce the resistance of the write word line and decrease memory write latency to the SRAM bit cell as a result. In certain exemplary aspects, the metal line pitch and minimum distance between metal lines of the SRAM bit cell can be maintained for maintaining fabrication compatibility with existing fabrication processes with decreasing the resistance of the write word line of the SRAM bit cell.

公开(公告)号：US11092646B1

公开(公告)日：2021-08-17

申请号：US16794105

申请日：2020-02-18

Applicant: QUALCOMM Incorporated

Inventor： Sonia Ghosh ,  Changho Jung ,  Chulmin Jung

IPC: G01R31/3181 ,  G01R31/317 ,  G01J1/18

Abstract: According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.

公开(公告)号：US20220102360A1

公开(公告)日：2022-03-31

申请号：US17038037

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Biradar ,  Sunil Sharma ,  Channappa Desai ,  Sonia Ghosh

IPC: H01L27/11 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  G11C11/419

Abstract: SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.

公开(公告)号：US09858988B1

公开(公告)日：2018-01-02

申请号：US15206018

申请日：2016-07-08

Applicant: QUALCOMM Incorporated

Inventor： Sonia Ghosh ,  Changho Jung

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227 ,  G11C11/418

Abstract: A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy wordline. The dummy wordline is configured to emulate at least one portion of the wordline. An apparatus is presented. The apparatus include a first memory having a first wordline coupled to a first number of memory cells. A second memory having a second wordline coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit to enable a memory operation. The timing circuit includes a delay stage corresponding to loading of a third number of memory cells. The third number is different from the first number.

公开(公告)号：US11289495B1

公开(公告)日：2022-03-29

申请号：US17038037

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Biradar ,  Sunil Sharma ,  Channappa Desai ,  Sonia Ghosh

IPC: H01L27/11 ,  G11C11/419 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/092

Abstract: SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.

公开(公告)号：US11222846B1

公开(公告)日：2022-01-11

申请号：US17002486

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Sunil Sharma ,  Rahul Biradar ,  Sonia Ghosh

IPC: H01L23/528 ,  H01L27/11 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/522

Abstract: Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exemplary aspects, the SRAM bit cell employs an increased width write word line based on a circuit cell layout area savings achieved by employing a reduced width read word line. Increasing the width of the write word line can reduce the resistance of the write word line and decrease memory write latency to the SRAM bit cell as a result. In certain exemplary aspects, the metal line pitch and minimum distance between metal lines of the SRAM bit cell can be maintained for maintaining fabrication compatibility with existing fabrication processes with decreasing the resistance of the write word line of the SRAM bit cell.

公开(公告)号：US10916275B1

公开(公告)日：2021-02-09

申请号：US16735539

申请日：2020-01-06

Applicant: QUALCOMM Incorporated

Inventor： Sonia Ghosh ,  Changho Jung

IPC: G11C7/12 ,  G11C8/16 ,  G11C7/08 ,  G11C11/419

Abstract: A method for operating a pseudo-dual port (PDP) memory is described. The method includes pre-charging bitline pairs BL and BLB coupled to unselected columns of the PDP memory according to a write operation during a pre-charge operation after a read operation of the PDP memory. The method also includes concurrently pulling-down a bitline pair BL and BLB coupled to a selected column of PDP memory according to the write operation.

公开(公告)号：US09905316B2

公开(公告)日：2018-02-27

申请号：US15225744

申请日：2016-08-01

Applicant: QUALCOMM Incorporated

Inventor： Sonia Ghosh ,  Changho Jung

IPC: G11C7/00 ,  G11C29/00 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C29/781 ,  G11C7/065 ,  G11C7/22 ,  G11C29/702 ,  G11C29/832 ,  G11C29/846 ,  G11C29/848

Abstract: A memory includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to select for their corresponding column or an immediately-subsequent column to their corresponding column.

公开(公告)号：US09685210B1

公开(公告)日：2017-06-20

申请号：US15205857

申请日：2016-07-08

Applicant: QUALCOMM Incorporated

Inventor： Sonia Ghosh ,  Changho Jung

IPC: G11C7/12 ,  G11C11/419 ,  G11C7/06 ,  G06F12/00

CPC classification number: G11C7/12 ,  G06F12/00 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1075 ,  G11C11/419 ,  G11C2207/002 ,  G11C2207/2209

Abstract: A memory includes a plurality of memory cells and a plurality of bitlines. Each of the plurality of bitlines is coupled to a corresponding one of the plurality of memory cells. A precharge circuit precharges each of the plurality of bitlines before a read operation and precharges all but one of the plurality of bitlines following the read operation. A write driver drives the one of the plurality of bitlines following the read operation. A method includes precharging each of a plurality of bitlines before a read operation. Each of the plurality of bitlines is coupled to a corresponding one of a plurality of memory cells. The method further includes precharging all but one of the plurality of bitlines following the read operation and driving the one of the plurality of bitlines following the read operation.