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公开(公告)号：US09183041B2
公开(公告)日：2015-11-10
申请号：US13624216
申请日：2012-09-21
发明人： Norbert Hagspiel , Matthias Klein
CPC分类号： G06F9/467 , G06F13/161
摘要： According to one aspect of the present disclosure a system and technique for input/output traffic backpressure prediction is disclosed. The system includes a processor unit and logic executable by the processor unit to: determine, for each of a plurality of memory transactions, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determine a median value based on the determined traffic values; determine whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicate a prediction of a backpressure condition.
摘要翻译： 根据本公开的一个方面，公开了一种用于输入/输出业务背压预测的系统和技术。 该系统包括处理器单元和可由处理器单元执行的逻辑，用于：对于多个存储器事务中的每一个，确定对应于用于执行各个存储器事务的时间的业务值; 响应于确定相应存储器事务的业务值，基于所确定的业务量确定中值; 确定连续中值是否递增; 并且响应于超过阈值的连续增加的中值的量，指示背压状态的预测。
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2.发明申请公开(公告)号：US20140025922A1
公开(公告)日：2014-01-23
申请号：US14034848
申请日：2013-09-24
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： An aspect includes a method for operating on translation look-aside buffers (TLBs) in a multiprocessor environment including a plurality of logical partitions as zones. The method includes concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones including the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones including the second zone. The second set of zones consists of separate zones from the first set of zones. Based on receiving the first quiesce request, only processors of the first set of zones are quiesced. Based on the processors of the first set of zones being quiesced, a first operation is performed on the TLBs. Based on the first operation being performed, the processors of the first set of zones are un-quiesced.
摘要翻译： 一个方面包括在包括多个逻辑分区作为区域的多处理器环境中对翻译后备缓冲器（TLB）进行操作的方法。 该方法包括同时从第一区域的第一处理器接收第一静默请求，以使包括第一区域的第一组区域的处理器静止，并从第二区域的第二处理器接收第二静默请求，以使第二区域的处理器静止 一组区域包括第二个区域。 第二组区域由与第一组区域分开的区域组成。 基于接收到第一个静默请求，只有第一组区域的处理器停顿。 基于处于静止状态的第一组区域的处理器，对TLB执行第一操作。 基于正在执行的第一操作，第一组区域的处理器是不静默的。
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公开(公告)号：US11354094B2
公开(公告)日：2022-06-07
申请号：US15827784
申请日：2017-11-30
IPC分类号： G06F7/24 , G06F7/16 , G06F9/30 , H03K19/177 , G06F13/16 , G06F9/54 , H03K19/17732 , G06F16/21 , G06F16/27 , G06F13/28
摘要： A sort device includes a compare unit on one level of a hierarchical structure that includes a plurality of levels. The compare unit to compare one beat of one record with another beat of another record to provide a winner beat. The sort device further includes another compare unit on another level of the hierarchical structure to provide a further beat to the compare unit, and a request pipe to be used to request that the other compare unit provide the further beat to the compare unit.
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公开(公告)号：US10423546B2
公开(公告)日：2019-09-24
申请号：US15806407
申请日：2017-11-08
摘要： A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.
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公开(公告)号：US20190163441A1
公开(公告)日：2019-05-30
申请号：US15827644
申请日：2017-11-30
摘要： Multi-cycle key compare units. A compare unit includes a comparator, additional compare logic and at least one pair of buffers which provide input to the comparator. The compare unit sorts variable length records in streaming mode without the need for complex state machines to maintain state relating to the comparing. A record may have a variable length key and optional variable length data. The record and/or the key is split into fixed, pre-defined lengths. The total key and record lengths are unknown to the comparator of the compare unit.
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公开(公告)号：US09767048B2
公开(公告)日：2017-09-19
申请号：US14862221
申请日：2015-09-23
CPC分类号： G06F13/102 , G06F13/20 , G06F13/4068
摘要： A data processing system is provided which includes a processor nest communicatively coupled to an input/output bus by a bus controller, and a service interface controller communicatively coupled to the processor nest. The system includes storage for storing commands for the bus controller and associated command data and resulting status data, the storage being communicatively coupled to the processor nest and the bus controller. The service interface controller is configured, in response to received service commands, to read and write the storage, to execute the command specified in the storage, to retrieve the result of the command, and to store the result in the storage.
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公开(公告)号：US20150154131A1
公开(公告)日：2015-06-04
申请号：US14551798
申请日：2014-11-24
CPC分类号： G06F13/28 , G06F12/0811 , G06F12/084 , G06F12/0868 , G06F12/0871 , G06F2212/1024 , G06F2212/6042
摘要： A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.
摘要翻译： 数据处理装置包括多个处理器核，共享处理器高速缓存，总线单元和总线控制器。 共享处理器高速缓存连接到每个处理器内核和主存储器。 总线单元通过总线控制器连接到共享处理器高速缓存器，用于向/从I / O设备传送数据。 为了进一步改进处理器高速缓存和I / O设备之间的数据传输速率，总线控制器被配置为响应于从处理器核心接收到描述符来执行对共享处理器高速缓存的直接存储器访问 根据描述符，经由总线单元将数据从共享处理器高速缓存传送到I / O设备。
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公开(公告)号：US20150149727A1
公开(公告)日：2015-05-28
申请号：US14090347
申请日：2013-11-26
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F12/0846 , G11C7/22 , G11C11/419 , G11C2207/2209
摘要： A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time.
摘要翻译： 描述了避免来自两个独立写入操作的单端口存储器设备中的写入冲突的方法。 来自第一写入操作的第一数据对象被划分为第一偶数子数据对象和第一奇数子数据对象。 来自第二写入操作的第二数据对象被划分为第二偶数子数据对象和第二奇数子数据对象。 当第一次写入操作和第二次写入操作同时发生时，第一偶数子数据对象被存储到第一单个端口存储器设备，而第二个奇数子数据对象被存储到第二单个端口存储器设备。 当第一写入操作和第二写入操作同时发生时，第二偶数子数据对象被存储到第一单个端口存储器件和第一奇数子数据对象到第二单个端口存储器件。
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公开(公告)号：US10936517B2
公开(公告)日：2021-03-02
申请号：US16451650
申请日：2019-06-25
IPC分类号： G06F12/084 , G06F13/28 , G06F12/0811 , G06F12/0868 , G06F12/0871
摘要： A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.
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公开(公告)号：US10936283B2
公开(公告)日：2021-03-02
申请号：US15827697
申请日：2017-11-30
IPC分类号： G06F7/00 , G06F7/24 , G06F13/16 , H03K19/177 , G06F9/54 , G06F9/30 , H03K19/17732 , G06F13/28
摘要： A logic device includes a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records. The compare unit includes a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record. The logic device further includes another compare unit on another level of the plurality of levels of the hierarchical structure. The other compare unit includes another buffer pair in which one or more other buffers of the other buffer pair are adapted to store a portion of a record. A size of the one or more other buffers of the other buffer pair is insufficient to store the entire record. The one compare unit and the other compare unit are adapted to sort a plurality of records.
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